Multimedia processor using variable length instructions with opcode specification of source operand as result of prior instruction
First Claim
1. A multimedia circuit, comprising:
- a plurality of arithmetic logic units (ALUs), each ALU having associated therewith a register to which an output datum of said ALU is stored; and
an instruction register, said instruction register accommodating first and second instructions, each instruction specifying an op-code, one of said ALUs and an operand op-code of said first instruction specifies as said operand source of said first instruction the result register associated with the ALU specified in said second instruction.
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Accused Products
Abstract
A media engine is disclosed herein which incorporates into a single chip structure the seven multimedia functions of video, 2D graphics, 3D graphics, audio, FAX/modem, telephony, and video-conferencing. In accordance with the present invention, a media engine includes a signal processor which shares a memory with the CPU of the host computer and also includes a plurality of control modules each dedicated to one of the seven multi-media functions. The signal processor retrieves from this shared memory instructions placed therein by the host CPU and in response thereto causes the execution of such instructions via one of the on-chip control modules. The signal processor utilizes an instruction register having a movable partition which allows larger than typical instructions to be paired with smaller than typical instructions. The signal processor reduces demand for memory read ports by placing data into the instruction register where it may be directly routed to the arithmetic logic units for execution and, where the destination of a first instruction matches the source of a second instruction, by defaulting the source specifier of the second instruction to the result register of the ALU employed in the execution of the first instruction.
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Citations
10 Claims
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1. A multimedia circuit, comprising:
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a plurality of arithmetic logic units (ALUs), each ALU having associated therewith a register to which an output datum of said ALU is stored; and an instruction register, said instruction register accommodating first and second instructions, each instruction specifying an op-code, one of said ALUs and an operand op-code of said first instruction specifies as said operand source of said first instruction the result register associated with the ALU specified in said second instruction. - View Dependent Claims (2, 3, 4, 5, 6)
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7. In a microprocessor, a method comprising the steps of:
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providing a plurality of arithmetic logic units (ALUs) each capable of executing an instruction and providing a datum in a register associated with each ALU; providing an instruction register designed for holding a plurality of said instructions, each instruction specifying an opcode, an operand source and one of said ALUs for executing said instruction; assigning each instruction in said instruction register to a selected one of said ALUs for execution; executing said instructions of said instruction register in their respective assigned ALUs and providing a result datum for each of said instructions and determining whether said opcode of an instruction specifies that said result datum of said instruction is to be stored in said operand source. - View Dependent Claims (8, 9, 10)
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Specification