Massively parallel processing system using two data paths: one connecting router circuit to the interconnect network and the other connecting router circuit to I/O controller

• US 5,864,738 A
• Filed: 03/13/1996
• Issued: 01/26/1999
• Est. Priority Date: 03/13/1996
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: CRAY Incorporated (Hewlett-Packard Enterprise Company)
• Inventors: Oberlin, Steven M., Kessler, Richard E., Scott, Steven L.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Ton, David
• Application Number:
  US08/614,859
• Time in Patent Office: 1,049 Days
• Field of Search: 395/558, 395/182.1, 395/200.3, 395/200.69, 395/858
• US Class Current: 709/239
• CPC Class Codes: G06F 12/0817 using directory methods
• CPC Class Codes: G06F 15/17375 One dimensional, e.g. linear array, ring
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors

Abstract

A system and method of transferring information between a peripheral device and an MPP system having an interconnect network and a plurality of processing nodes. Each processing element includes a processor, local memory and a router circuit connected to the interconnect network, the processor and the local memory. Each router circuit includes means for transferring data between the processor and the interconnect network and means for transferring data between the local memory and the interconnect network. An I/O controller is connected to a plurality of the router circuits. Data is then read from the peripheral device and transferred through the I/O controller to local memory of one of the processing elements.

Claims

1. A massively parallel processing system, comprising:

an interconnect network;

a plurality of processing nodes, wherein each processing node includes;

a processor;

local memory; and

a router circuit connected to the interconnect network, the processor and the local memory, wherein the router circuit includes first and second data paths, wherein the router circuit transfers data between the processor and the interconnect network and between the local memory and the interconnect network over said first data path; and

a plurality of I/O controllers, including a first I/O controller, wherein each I/O controller is connected to the second data path of a plurality of the router circuits and wherein each router circuit further includes I/O routing means for transferring data between the I/O controller to which the router circuit is connected and local memory of any of the plurality of processing nodes.

2. The system according to claim 1 wherein one of the local memories includes a first memory location and wherein the router circuit further includes an external registers circuit, wherein the external registers circuit includes:

a plurality of external registers connected to the processor via a data bus;

an address translator for calculating, based on an index written to the data bus, an address associated with the first memory location; and

transfer means, connected to the plurality of external registers, for transferring data between the first memory location and one of the plurality of external registers.

3. The system according to claim 2 wherein the router circuit further includes an integrated address centrifuge.

4. The system according to claim 1 wherein the I/O routing means includes means for forwarding to the I/O controller a message packet received by the router circuit.

5. A massively parallel processing system, comprising:

an interconnect network;

a plurality of processing nodes, wherein each processing node includes;

a processor;

local memory; and

a router circuit connected to the interconnect network, the processor and the local memory, wherein the router circuit includes first and second data paths, wherein the router circuit transfers data between the processor and the interconnect network and between the local memory and the interconnect network over said first data path;

a peripheral device; and

a plurality of I/O controllers, including a first I/O controller, wherein each I/O controller is connected to the second data path of a plurality of the router circuits and wherein each router circuit further includes I/O routing means for transferring data between the I/O controller to which the router circuit is connected and local memory of any of the plurality of processing nodes

a plurality of I/O controllers, including a first I/O controller, wherein each I/O controller is connected to a plurality of router circuits, wherein each router circuit further includes means for transferring data between the I/O controller to which the router circuit is connected and local memory of any of the plurality of processing nodes and wherein the first I/O controller includes peripheral interface means for transferring data from the peripheral device to the local memory on one of the plurality of processing nodes.

6. The system according to claim 5, wherein the peripheral interface means includes a serial channel connected to the peripheral device and to one of the plurality of I/O controllers.

7. The system according to claim 5 wherein one of the local memories includes a first memory location and wherein the router circuit further includes an external registers circuit, wherein the external registers circuit includes:

a plurality of external registers connected to the processor via a data bus;

an address translator for calculating, based on an index written to the data bus, an address associated with the first memory location; and

transfer means, connected to the plurality of external registers, for transferring data between the first memory location and one of the plurality of external registers.

8. The system according to claim 7 wherein the router circuit further includes an integrated address centrifuge.

9. The system according to claim 5 wherein the I/O routing means includes means for forwarding to the I/O controller a message packet received by the router circuit.

10. A method of transferring data between a peripheral device and a massively parallel processing system having an interconnect network and a plurality of processing nodes, wherein each processing node includes a processor, local memory and a router circuit connected to the interconnect network, the processor and the local memory, wherein the router circuit includes a first and a second data path, wherein the router circuit transfers data between the processor and the interconnect network and between the local memory and the interconnect network over said first data path:

providing an I/O controller;

connecting the I/O controller to the second data path of a plurality of router circuits;

reading data from the peripheral device;

transferring the data read from the peripheral device from the I/O controller to one of the plurality of router circuits connected to the I/O controller; and

transferring the data read from the peripheral device from the one of the plurality of router circuits connected to the I/O controller across the interconnect network to the local memory of one of the plurality of processing nodes.

11. The method according to claim 10, wherein the step of reading includes the steps of formatting a packet containing the data read from the peripheral device and sending the packet over a serial channel to the I/O controller.