Method and apparatus of programming FPGA devices through ASIC devices

• US 5,867,037 A
• Filed: 10/24/1996
• Issued: 02/02/1999
• Est. Priority Date: 10/24/1996
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Tra, An Xuan, Capps, Louis Bennie Jr., Iachetta, Richard Nicholas Jr.
• Primary Examiner(s): SANTAMAURO, JON P
• Application Number:
  US08/736,303
• Time in Patent Office: 831 Days
• Field of Search: 326/38-39, 364/489-490
• US Class Current: 326/38
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A method and apparatus for receiving and transmitting programming data through an application specific integrated circuit is provided. In a first embodiment, the application specific integrated circuit comprises a main circuit, at least two input/output (I/O) mechanisms connected to the main circuit for transferring data into and out of the main circuit and a mechanism for receiving and transmitting the programming data. The mechanism for transmitting the programming data includes a tri-state buffer that is activated by a programming enable signal. In a second embodiment, the input and output of the buffer are multiplexed with the two I/O mechanisms connected to the main circuit.

Claims

1. An application specific integrated circuit, (ASIC), having a plurality of first input/output (I/O) means comprising:

a means for receiving and transmitting programming data;

a first buffer means having second I/O means, said first buffer means being a tri-state buffer for temporarily storing said programming data, said first buffer means being activated by a programming signal for transmitting said programming data via said second output means; and

means for multiplexing said second I/O means with said first I/O means.

2. The application specific integrated circuit of claim 1 wherein said multiplexing means includes a second and third buffer means having third and fourth input and output means, respectively, said third input means of said second buffer and said fourth output means of said third buffer being connected to said second input means of said first buffer, said third output means of said second buffer and said fourth input means of said third buffer being connected to said a main circuit in said ASIC, said second and third buffers being activated by an inverted signal of said programming signal.

3. The application specific integrated circuit of claim 2 wherein said multiplexing means further includes a fourth and fifth buffers having a fifth and sixth input and output means, said fifth output means of said fourth buffer and said sixth input means of said fifth buffer being connected to said second output means of said first buffer, said fifth input means of said fourth buffer and said sixth output means of said fifth buffer being connected to said main circuit, said second buffer being activated by said inverted programming signal.

4. A method of transferring programming data from an application specific integrated circuit (ASIC), said ASIC having at least one input for receiving data and one output for transmitting data, said method comprising the steps of:

receiving said programming data into said application specific integrated circuit;

storing said programming data into a buffer; and

using a programming signal for activating said buffer for transferring said programming data, said buffer having an input for receiving and an output for transmitting said programming data; and

multiplexing said buffer input with said at least one ASIC input and said buffer output with said at least one ASIC output.