System and method for creating and validating structural description of electronic system from higher-level and behavior-oriented description

• US 5,867,399 A
• Filed: 04/21/1997
• Issued: 02/02/1999
• Est. Priority Date: 04/06/1990
• Status: Expired due to Term

• Current Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Watkins, Daniel R., Rostoker, Michael D.
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US08/847,930
• Time in Patent Office: 652 Days
• Field of Search: 364/488, 364/489, 364/490
• US Class Current: 716/102
• CPC Class Codes: G01R 31/31704 Design for test; Design verification concerning scan tests G01R31/318583; computer-aided design G06F30/00
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation
• CPC Class Codes: G06F 2111/12 Symbolic schematics
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation

Abstract

A system for interactive design and simulation of an electronic circuit allowing a user to design a circuit by graphical entry and to view full or partial simulation and design results simultaneously, on a single display window. The user is able to define the form of a display of speed, delay, loading, symbols, simulation input and/or output values on each node and any path of the design. Simulation may be user-defined or other process time. The user is further able to view any information relevant to any object in the design at any level of design abstraction, and is able to view multiple levels of design abstraction simultaneously and to display information common to the various representations.

Claims

1. An integrated electronic computer aided design system, comprising:

a schematic editor for allowing a user of said system to graphically enter and modify a schematic design displayed on a display screen, and for generating a net-list that includes information relating to the net of said schematic design;

a logic compiler for receiving said net-list and accessible to a component database for generating an object file that includes information relating to either layout, verification or simulation of said schematic design;

a logic verifier for checking said schematic diagram for design errors and generating an error indication when said design errors are located in said schematic design;

a logic simulator for receiving the information in said object file and generating a simulation results responsive to a set of initial conditions; and

a layout generator for generating layout data from which a semiconductor chip may be laid out.

2. The integrated electronic computer aided design system of claim 1, wherein said logic verifier is capable of checking said schematic design for design errors that include multiple outputs connected together and overloaded signal paths.

3. The integrated electronic computer aided design system of claim 1, wherein said logic compiler is responsive to said schematic editor in a manner that changes to said schematic design causes said logic compiler to re-generate said object file to reflect said changes to said schematic design.

4. The integrated electronic computer aided design system of claim 1, wherein said logic simulator is capable of receiving from said schematic editor initial and signal data information and a request for a simulation run instruction.

5. The integrated electronic computer aided design system of claim 1, wherein said logic simulator is capable of providing said simulation result in a data structure for storing in a memory device.

6. The integrated electronic computer aided design system of claim 1, wherein said schematic editor causes said logic compiler to re-generate said object file when an object is added, modified or deleted in said schematic design, and when a connection is made, changed or removed in said schematic design.

7. The integrated electronic computer aided design system of claim 1, wherein said schematic editor provides for a user to force selected conditions to a selected net in said schematic design.

8. The integrated electronic computer aided design system of claim 1, wherein said system provides for a user to select a portion of said schematic design for analysis.

9. The integrated electronic computer aided design system of claim 8, wherein said schematic editor generates a subset net-list that includes information relating to the net of said portion of said schematic design, and wherein said logic compiler generates a subset object file that includes information relating to either layout, verification or simulation of said portion of said schematic design.

10. The integrated electronic computer aided design system of claim 8, wherein the schematic editor can display multiple levels of abstraction of said schematic design on said display screen.

11. The integrated electronic computer aided design system of claim 1, wherein said schematic editor provides a state table in a portion of said display screen which identifies the simulated signals of said schematic design.

12. The integrated electronic computer aided design system of claim 1, further including a sub-system for gathering and condensing information relevant to said schematic design.

13. The integrated electronic computer aided design system of claim 1, wherein said schematic editor and said logic verifier are linked in a manner that said schematic editor is capable of displaying design errors located by said logic verifier at portions of said schematic design causing said design errors.

14. The integrated electronic computer aided design system of claim 1, further including an expert system that analyzes said schematic design and design errors located by said logic verifier, and provides suggestion to a user for alterations or corrections to said schematic design.

15. A method of creating and validating a circuit design from a behavior-oriented description of said circuit design, comprising:

specifying a desired behavior for said circuit design in a high-level language;

partitioning said circuit design into a plurality of functional block representations;

synthesizing a component design for each of said plurality of functional block representations and generating a net-list for said component design;

performing a gate-level simulation of said component design; and

comparing the result of said gate-level simulation of said component design with said desired behavior.

16. The method of claim 15, wherein the step of specifying said desired behavior for said circuit is performed using a VHDL hardware description language.

17. The method of claim 15, wherein said step of partitioning said circuit design includes the steps of:

determining a design space available criteria for said circuit design;

determining a high-level timing criteria for said circuit design;

placing constraints on said circuit design to meet both said high-level timing and design space available criterias; and

partitioning said circuit design in according to said constraints on said circuit design.

18. The method of claim 15, wherein the step of synthesizing a component design for each of said plurality of functional block representations includes the steps of:

directing a first set of said functional block representations that has highly regular structures to a specific synthesis tool; and

directing a second set of said functional block representations that has random or unstructured logic to a more general synthesis program.

19. The method of claim 15, further including the step of back-annotating to ensure that other physical limitations, including capacitive loads and parasitics, are not exceeded.