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System and method for creating and validating structural description of electronic system from higher-level and behavior-oriented description

  • US 5,867,399 A
  • Filed: 04/21/1997
  • Issued: 02/02/1999
  • Est. Priority Date: 04/06/1990
  • Status: Expired due to Term
First Claim
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1. An integrated electronic computer aided design system, comprising:

  • a schematic editor for allowing a user of said system to graphically enter and modify a schematic design displayed on a display screen, and for generating a net-list that includes information relating to the net of said schematic design;

    a logic compiler for receiving said net-list and accessible to a component database for generating an object file that includes information relating to either layout, verification or simulation of said schematic design;

    a logic verifier for checking said schematic diagram for design errors and generating an error indication when said design errors are located in said schematic design;

    a logic simulator for receiving the information in said object file and generating a simulation results responsive to a set of initial conditions; and

    a layout generator for generating layout data from which a semiconductor chip may be laid out.

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