High density non-volatile flash memory without adverse effects of electric field coupling between adjacent floating gates

• US 5,867,429 A
• Filed: 11/19/1997
• Issued: 02/02/1999
• Est. Priority Date: 11/19/1997
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Chen, Jian, Fong, Yupin
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): PHAN, TRONG Q
• Application Number:
  US08/974,276
• Time in Patent Office: 440 Days
• Field of Search: 365/185.33, 365/185.21, 365/185.26
• US Class Current: 365/185.33
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 2029/5002 Characteristic
• CPC Class Codes: G11C 2211/5649 Multilevel memory with plate line or layer, e.g. in order to lower programming voltages
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50004 of threshold voltage
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Electric field coupling between floating gates of a high density flash EEPROM cell array has been found to produce errors in reading the states of the cells, particularly when being operated with more than two storage states per cell. The effect of this coupling is overcome by placing a conductive shield or insulating material with a low dielectric constant between adjacent floating gates, and/or by compensating for the coupling when reading the states of the cells.

Claims

1. A flash EEPROM, comprising:

an array of memory cells that individually include a source and drain bounding a semi-conductive channel in a substrate, a floating gate positioned adjacent the substrate surface channel with a first dielectric layer therebetween, and one or more operating gates adjacent the floating gate with a corresponding one or more dielectric layers therebetween,

a source of controllable voltages connected to the one or more operating gates, the source and the drain,

sensing circuits connectable to the array to determine a quantity related to one of two or more adjacent programmable floating gate charge level ranges defining respective two or more states into which addressed ones of the individual cells are programmed,

adjacent floating gates being positioned close enough together such that a change of charge level between one of the two or more charge level ranges on one of two adjacent cells would cause an erroneous reading of at least one of the states of the other of the two adjacent cells if an insulating material having a dielectric constant in excess of 3.8 extended entirely between the adjacent floating gates, and

elements positioned between said adjacent floating gates to reduce cross-talk therebetween in order to reduce the erroneous readings.

2. The flash EEPROM of claim 1, wherein said elements positioned between said adjacent floating gates are electrically conductive and positioned to provide an electric field shield between the adjacent floating gates.

3. The flash EEPROM of claim 2, wherein the conductive elements are other than the one or more operating gates.

4. The flash EEPROM of claim 1, wherein said elements are a dielectric material having a dielectric constant of less than 2.5 in order to reduce an electric field coupling between the adjacent floating gates.

5. The flash EEPROM of any one of claims 1-4, wherein said one or more operating gates includes only a control gate.

6. The flash EEPROM of any one of claims 1-4, wherein said one or more operating gates includes only a control gate and an erase gate.

7. The flash EEPROM of any one of claims 1-4, wherein the sensing circuits determine a quantity related to one of three or more adjacent programmable floating gate charge level ranges defining respective three or more states.

8. The flash EEPROM of claim 7, wherein said one or more operating gates includes only a control gate.

9. The flash EEPROM of claim 7, wherein said one or more operating gates includes only a control gate and an erase gate.

10. The flash EEPROM of any one of claims 1-4, wherein the sensing circuits determine a quantity related to one of eight or more adjacent programmable floating gate charge level ranges defining respective three or more states.

11. A flash EEPROM, comprising:

an array of rows and columns of memory cells that individually include a source and drain bounding a semi-conductive channel in a surface of a substrate, a floating gate positioned adjacent the substrate surface channel with a first dielectric layer therebetween, and one or more operating gates adjacent the floating gate with a corresponding one or more dielectric layers therebetween,

a source of controllable voltages connected to the one or more operating gates, the source, the drain, and the substrate,

the one or more operating gates providing a shield between adjacent floating gates in a direction of one of the rows or columns,

sensing circuits connectable to the array to determine a quantity related to one of three or more adjacent programmable floating gate charge level ranges defining respective three or more states into which addressed ones of the individual cells are programmed,

adjacent floating gates being positioned close enough together in a direction of the other of the rows or columns such that a change in charge level within one of the three or more charge level ranges on one of two adjacent cells would cause an erroneous reading of at least one of the states of the other of the two adjacent cells if no shield is provided therebetween, and

conductive elements other than the one or more operating gates positioned in between the floating gates in a direction of the other of the rows or columns, thereby to provide a shield that substantially eliminates an erroneous reading of the states of adjacent cells.

12. The flash EEPROM of claim 11, wherein said one or more operating gates includes only a control gate.

13. The flash EEPROM of claim 11, wherein said one or more operating gates includes only a control gate and an erase gate.

14. The flash EEPROM of any one of claims 11-13, wherein the sensing circuits determine a quantity related to one of eight or more adjacent programmable floating gate charge level ranges defining respective three or more states.

15. A flash EEPROM, comprising:

an array of rows and columns of memory cells that individually include a source and drain bounding a semi-conductive channel in a surface of a substrate, a floating gate positioned adjacent the substrate surface channel with a first dielectric layer therebetween, and one or more operating gates adjacent the floating gate with a corresponding one or more dielectric layers therebetween,

a source of controllable voltages connected to the one or more operating gates, the source, the drain and the substrate,

the one or more operating gates providing a shield between adjacent floating gates in a direction of one of the rows or columns,

sensing circuits connectable to the array to determine a quantity related to one of three or more adjacent programmable floating gate charge level ranges defining respective three or more states into which addressed ones of the individual cells are programmed,

adjacent floating gates being positioned close enough together in a direction of the other of the rows or columns such that a change in charge level within one of the three or more charge level ranges on one of two adjacent cells would cause an erroneous reading of at least one of the states of the other of the two adjacent cells if an insulating material having a dielectric constant in excess of 3.8 extended entirely between the adjacent floating gates, and

at least a portion of a distance between the adjacent floating gates in a direction of the other of the rows or columns including a dielectric material having a dielectric constant of less than 3.5, thereby to reduce an electric field coupling between the adjacent floating gates that substantially eliminates an erroneous reading of the states of adjacent cells.

16. The flash EEPROM of claim 15, wherein said one or more operating gates includes only a control gate.

17. The flash EEPROM of claim 15, wherein said one or more operating gates includes only a control gate and an erase gate.

18. The method of claim 15, wherein the dielectric material positioned between the adjacent floating gates has a dielectric constant of less than 2.5.

19. The flash EEPROM of any one of claims 15-18, wherein the sensing circuits determine a quantity related to one of eight or more adjacent programmable floating gate charge level ranges defining respective three or more states.

20. In a flash EEPROM system that includes an array of rows and columns of memory cells that individually have a floating gate and one or more operating gates adjacent the floating gate, and a circuit that reads the states of an addressed plurality of the array of cells with respect to two or more breakpoint levels defining three or more memory states of the individual cells, a method of reading the states of an addressed set of the cells, comprising:

reading the states of a plurality of cells adjacent to and in electric field communication with the addressed set of cells,

determining an effect of charge levels on the floating gates of said adjacent cells upon the states read from the addressed set of cells, and

adjusting the read states of the addressed set of cells to take into account the effect of charge levels on the floating gates of the adjacent cells.

21. The method of claim 20, wherein adjusting the read states of the addressed set of cells includes shifting the breakpoint levels of the circuit that reads the states of the addressed plurality of cells.

22. The method of claim 21, wherein determining an effect of charge levels on the floating gates of the adjacent cells upon the states read from the addressed set of cells includes:

reading the states of the adjacent cells with reference breakpoint levels in the circuit that reads the states of addressed cells, and

utilizing an electric field coupling ratio between individual ones of the addressed and adjacent plurality of cells to determine a proportion of charge on the adjacent cells that is reflected into the readings of the addressed set of cells.

23. The method of claim 20 accomplished a plurality of times during programming of the addressed set of cells to verify their newly programmed states.