Shared bitline heterogeneous memory

• US 5,867,443 A
• Filed: 08/17/1995
• Issued: 02/02/1999
• Est. Priority Date: 08/17/1995
• Status: Expired due to Fees

• Current Assignee: Air Force Department of United States of America
• Original Assignee: United States Of America As Represented By The Secretary Of The Air Force
• Inventors: Linderman, Richard W.
• Primary Examiner(s): Dinh, Son T.
• Application Number:
  US08/528,620
• Time in Patent Office: 1,265 Days
• Field of Search: 365/154, 365/156, 365/228, 365/230.03, 365/203
• US Class Current: 365/228
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 11/412 using field-effect transistors only

Abstract

A five-transistor static Random Access Memory (SRAM) cell accessed by a single bitline merged with heterogeneous memories, such as ROMs, EPROMs, EEPROMs, and DRAMs. Combined ROM and RAM cells have been included within a high performance signal processor. Advantages include area and power dissipation savings resulting from shared column bitlines, associated column decoders, and column sense amplifiers. This eliminates circuit duplication.

Claims

1. A memory system comprising:

at least one shareable data signal line that extends between heterogeneous memory devices;

at least one memory cell connected to said at least one shareable data signal line for storing a data signal; and

means for transferring a stored data signal from said at least one memory cell to said at least one shareable data signal line.

2. A memory system as defined in claim 1 wherein each data signal line is a data bitline;

said at least one memory cell, for storing a databit signal, is a one of connected to and disconnected from said data bitline;

said means for transferring is effective to transfer a stored databit signal from said at least one memory cell to said data bitline; and

said means for transferring is further effective to transfer a stored databit signal from said data bitline to said at least one memory cell.

3. A memory system as defined in claim 2 wherein said data bitline extends from at least one memory cell in a RAM array to at least one memory cell in a ROM array.

4. A memory system as defined in claim 2 for ROM operation wherein:

said at least one memory cell includes a field effect transistor;

said field effect transistor is connected to said data bitline to store a bit value of 1; and

said field effect transistor is disconnected from said data bitline to store a bit value of 0.

5. A memory system as defined in claim 2, said memory system being effective for ROM operation, wherein:

said at least one memory cell includes a field effect transistor connected to said data bitline to store a bit value of 1; and

said data bitline has a default bit value of 0.

6. A memory system as defined in claim 2, said memory system being effective for RAM operation, wherein:

said means for transferring includes a read voltage and a write voltage;

said at least one memory cell comprises a bidirectional access switch connecting said data bitline to a pair of cross-coupled CMOS inverters;

said bidirectional access switch is operated from a word line driven by a CMOS inverter and an N-MOS transistor; and

said N-MOS transistor acts against said CMOS inverter to produce said read voltage lower than said write voltage.

7. A memory system as defined in claim 6 wherein:

said write voltage placed on said word line is effective for causing said databit signal on said data bitline to be transferred to said memory cell; and

said read voltage placed on said word line is effective for causing said databit signal to be transferred from said memory cell onto said data bitline.

8. The method of forming a memory system comprising the steps of:

(a) providing a data bitline that extends among heterogeneous memory devices;

(b) storing a data bit by connecting a cross-coupled memory cell to said data bitline by means of bidirectional access switch;

(c) transferring a stored data bit from said at least one memory cell to said data bitline, or to said at least one memory cell from said data bitline;

(d) connecting said data bitline to a write buffer that includes a data bus bit signal inverter connected to a transmission gate formed by parallel connected field-effect transistors activatable by an input write control signal and connected to at least one access switch; and

(e) connecting a pre-charge field effect transistor to said data bitline, thereby facilitating the interconnection of said heterogenous memory devices and bringing said data bitline to a voltage that enables a fast read of said stored data bit.

9. The method of forming a memory system as defined in claim 8 comprising the further steps of:

(f) operating said bidirectional access switch from a word line driven by a CMOS inverter and an N-MOS transistor; and

(g) forming a read voltage by said N-MOS transistor acting against said CMOS inverter to produce a lower voltage, thereby enabling said read voltage to be lower than a write voltage.

10. The method of forming a memory system as defined in claim 8 comprising the further steps of:

(h) extending said data bitline from said memory cell in a RAM array to a ROM array through a field-effect transistor;

thereby enabling simultaneous operation of said RAM and ROM arrays; and

(i) connecting the capacitance of said data bitline to said RAM array only when reading, whereby charge is saved and energy dissipation reduced.

11. The method of using a memory system comprising the steps of:

(a) providing a shareable data signal line that extends among heterogeneous devices;

(b) connecting memory cells to said data line for storing data signals; and

(c) transferring stored data signals between said memory cells and said data signal line.