Method and apparatus for testing an integrated circuit including the step/means for storing an associated test identifier in association with integrated circuit identifier for each test to be performed on the integrated circuit
First Claim
Patent Images
1. A method for testing a plurality of integrated circuits, including the steps of:
- performing a plurality of tests on the plurality of integrated circuits;
identifying integrated circuits that failed at least one of the plurality of tests and identifying tests failed by the integrated circuits; and
repeating at least one identified failed test on the identified integrated circuits.
6 Assignments
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Accused Products
Abstract
A method and apparatus for testing semiconductor memory chips, such as DRAMs, having a plurality of memory cells or bits. Each memory chip has a unique identifier stored in a database. Tests are performed on the memory chips and when a memory chip fails a test, the memory chip is placed in a repair bin and a test identifier is stored in the database in association with the memory chip identifier. In order to repair the memory chip, failed tests are read out of the database and such tests are again performed on the failed memory chip in order to determine which memory cell in the memory chip is faulty. The failed memory cells are then repaired.
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Citations
34 Claims
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1. A method for testing a plurality of integrated circuits, including the steps of:
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performing a plurality of tests on the plurality of integrated circuits; identifying integrated circuits that failed at least one of the plurality of tests and identifying tests failed by the integrated circuits; and repeating at least one identified failed test on the identified integrated circuits. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for testing an integrated circuit having an array of memory cells and an associated integrated circuit identifier stored in a memory, the method including the steps of:
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performing at least one test on the integrated circuit, each performed test having an associated test identifier; determining whether the integrated circuit passed each of the performed tests; storing an associated test identifier in the memory in association with the integrated circuit identifier for each performed test which the integrated circuit did not pass; reading one or more test identifiers stored in the memory associated with the integrated circuit identifier; and repeating at least one test associated with the one or more read test identifiers for the integrated circuit. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. An apparatus for testing a plurality of integrated circuits, including:
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means for performing a plurality of tests on the plurality of integrated circuits; means for identifying integrated circuits that failed at least one of the plurality of tests and identifying tests failed by the integrated circuits; and means for repeating at least one identified failed test on the identified integrated circuits. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26)
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27. An apparatus for testing an integrated circuit having an array of memory cells and an associated integrated circuit identifier stored in a memory, including:
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means for performing at least one test on the integrated circuit, each performed test having an associated test identifier; means for determining whether the integrated circuit passed each performed test; means for storing an associated test identifier in the memory in association with the integrated circuit identifier for each performed test which the integrated circuit did not pass; means for reading one or more test identifiers stored in the memory associated with the integrated circuit identifier; and means for repeating at least one test associated with the one or more read test identifiers for the integrated circuit. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34)
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Specification