Testable programmable gate array and associated LSSD/deterministic test methodology

• US 5,867,507 A
• Filed: 12/12/1995
• Issued: 02/02/1999
• Est. Priority Date: 12/12/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Worth, Brian, Gould, Scott Whitney, Keyser, Frank Ray III, Botala, Sally, Beebe, Wayne Kevin, Palmer, Ronald Raymond, Larsen, Wendell Ray
• Primary Examiner(s): DeCady, Albert
• Assistant Examiner(s): Iqbal, Nadeem
• Application Number:
  US08/570,846
• Time in Patent Office: 1,148 Days
• Field of Search: 371/22.3, 371/22.2, 371/22.1, 371/22.5, 371/25.1, 371/22.31, 371/22.32, 371/22.34, 371/27.5, 371/27.7, 364/488, 364/489, 364/490, 326/16, 326/37-39, 307/465, 395/183.06, 395/183.19, 324/765
• US Class Current: 714/726
• CPC Class Codes: G01R 31/318519 Test of field programmable gate arrays [FPGA]
• CPC Class Codes: G01R 31/318558 Addressing or selecting of subparts of the device under test

Abstract

A programmable gate array includes test subsystems for testing various functional subsystems of the programmable gate array. A sequence of test methods, employing the test subsystems, test the functionality of the programmable gate array, taking into account the interdependencies of the various subsystems and accordingly enabling fault isolation therein.

Claims

1. An improved testable field programmable gate array, FPGA, having:

a plurality of I/O ports;

I/O functional signal lines coupled to associated I/O ports of said plurality of I/O ports;

a plurality of programmable operating units providing particular logic circuits in accordance with associated logic configuration data;

a plurality of programmable interconnects interconnecting the I/O functional signal lines and programmable logic units of the plurality of programmable operating units in accordance with associated routing configuration data;

a plurality of memory cells associated with the respective plurality of programmable logic units and plurality of programmable interconnects, designated memory cells of the plurality of memory cells retaining the associated logic configuration data and routing configuration data; and

configuration logic having inputs receiving memory request signals, the configuration logic providing access to memory cells of the plurality of memory cells in accordance with the memory request signals;

wherein the improvement of the testable field programmable gate array includes test circuitry comprising;

first LSSD scan registers disposed as a boundary scan chain across the I/O functional signal lines, said first LSSD scan registers providing selective coupling into associated I/O functional signal lines for enabling serial scan access to, and functional verification of, the I/O functional signal lines and associated I/O ports;

second LSSD scan registers disposed as a scan chain about given segments of the configuration logic for providing serial scan access to, and enabling functional verification of, the configuration logic; and

third LSSD scan registers providing interconnect scan chains disposed along the programmable interconnects, the third LSSD scan registers providing selective coupling into respective programmable interconnects for enabling serial scan access to and functional verification of the programmable interconnects.

2. An improved FPGA according to claim 1, wherein the third LSSD scan registers have primary outputs selectively coupled to respective programmable interconnects in accordance with latch configuration data retained in associated memory cells of the plurality of memory cells.

3. An improved FPGA according to claim 1, wherein the test circuitry further comprises a control register programmable via a control register portion of the boundary scan chain, said control register providing control signals for controlling certain features of the FPGA.

4. An improved FPGA according to claim 3, wherein said boundary scan chain includes a reduced scan chain configuration selectively enabled in accordance with a control signal of said control signals provided by said control register.

5. An improved FPGA according to claim 4, wherein said reduced scan chain configuration consists of said control register portion alone.

6. An improved FPGA according to claim 3, wherein said control register provides a receive inhibit control signal for selectively inhibiting select I/O functional signal lines from propagating signals of associated I/O ports into the FPGA.

7. An improved FPGA according to claim 3, wherein said control register provides a driver inhibit control signal for selectively inhibiting select I/O ports from receiving certain signals from within the FPGA.

8. An improved FPGA according to claim 3, wherein given dedicated I/O ports of said plurality of I/O ports are dedicated, as non-functional I/O ports, for receiving test enable signals;

and

certain other I/O ports serve, in one mode of operation, as functional I/O ports, and are selectively reconfigurable in accordance with said test enable signal to serve alternatively, in a test mode of operation, as direct inputs for receiving certain control signals of said control signals directly from outside the FPGA, instead of said certain control signals being provided indirectly via said control register and associated boundary scan chain.

9. An improved FPGA according to claim 3, wherein said control register provides receiver/driver control signals for controlling interfacing functionality between said I/O functional signal lines and associated I/O ports.

10. An improved FPGA according to claim 9, wherein given dedicated I/O ports of said plurality of I/O ports are dedicated, as non-functional I/O ports, for receiving test enable signals;

and

certain other I/O ports serve, in one mode of operation, as functional I/O ports for interfacing select signal lines of said I/O functional signal lines, and are selectively reconfigurable, in accordance with said test enable signals, to serve alternatively, in a test mode of operation, as direct inputs for receiving receiver/driver controls signals directly from outside the FPGA, instead of said receiver/driver control signals being provided indirectly via said control register and associated control register portion of the boundary scan chain.

11. An improved testable FPGA according to claim 1, further comprising a tester having:

means for providing a test vector;

scan means for scanning the test vector serially into the second LSSD scan registers and applying the test vector to associated segments of the configuration logic;

capture means for providing appropriate clocking for capturing result data, as effected by the configuration logic after appropriate processing of the applied test vector, into the second LSSD scan registers;

said scan means being further operative for scanning the captured data serially out of the second LSSD scan registers; and

a fault detector for comparing the result data as scanned out to predetermined result data for determining functionality of the configuration logic.

12. An improved testable FPGA according to claim 1, wherein the plurality of programmable operating units are disposed across an array in rows and columns;

the plurality of programmable interconnects comprise multiple row buses and multiple column buses disposed across the array proximate respective rows and columns of the programmable operating units;

the plurality of programmable interconnects further comprise a plurality of programmable switch units that selectively subdivide select buses of the row buses and the column busses into associated bus segments in accordance with switch configuration data in designated memory cells of the plurality of memory cells;

each LSSD scan register of the third LSSD scan registers being incorporated with an associated switch unit of the plurality of programmable switch units; and

the LSSD scan registers of the switch units of associated row buses and column buses establishing respective row and column interconnect scan chains.

13. A method of testing an FPGA comprising:

(a)(1) providing first LSSD scan registers as a boundary scan chain around an I/O boundary of the FPGA;

(2) applying a known I/O test vector to the I/O boundary of the FPGA;

(3) latching data of the I/O boundary as latched data into the boundary scan chain;

(4) scanning data serially out of the boundary scan chain and retrieving the latched data of the I/O boundary;

(5) comparing the retrieved data with the known I/O test vector; and

(6) when the retrieved data does not correspond to the I/O test vector, reporting a fault;

(b)(1) providing second LSSD scan registers as a configuration scan chain for testing configuration logic of the FPGA, the configuration logic being operative for accessing memory cells of the FPGA in accordance with memory request signals;

(2) scanning a configuration test vector into the configuration scan chain;

(3) applying the configuration test vector of the configuration scan chain to the configuration logic;

(4) latching data, as effected by the configuration logic in response to the applied configuration test vector, into the configuration scan chain;

(5) scanning data serially out of the configuration scan chain and retrieving therefrom the data effected by the configuration logic;

(6) comparing the retrieved data with predetermined result data per the applied configuration test vector; and

(7) when the retrieved data does not correspond to the predetermined result data as associated with the applied configuration test vector, reporting a fault; and

(c)(1) providing third LSSD scan registers as interconnect scan chains configured within select programmable interconnects of the FPGA;

(2) configuring a first set of interconnects of the programmable interconnects of the FPGA between respective LSSD scan registers of said interconnect scan chains;

(3) scanning an interconnect test vector serially into a select input interconnect scan chain of said repeater scan chains and applying the interconnect test vector to an input side of the first set of interconnects;

(4) latching data from an output side of the first set of interconnects into a select output interconnect scan chain of said interconnect scan chains;

(5) scanning data serially out of the select output interconnect scan chain and retrieving therefrom the data as latched from the output side of the first set of interconnects;

(6) comparing the retrieved data with the interconnect test vector; and

(7) when the retrieved data does not correspond to the interconnect test vector, reporting a fault.

14. A method according to claim 13, further comprising steps for testing configuration memory cells of the FPGA including:

(d)(1) writing first known data to a given memory cell of said configuration memory cells as associated with configuring a given programmable resource of the FPGA;

(2) subsequently, retrieving data from the given memory cell;

(3) comparing the retrieved data to the first known data; and

(4) when the retrieved data does not correspond to the first known data, reporting a fault.

15. A method according to claim 14, further comprising a step of:

(d)(5) repeating steps (d)(1)-(d)(4) employing second known data which is the complement of the first known data.

16. A method according to claim 15, further comprising repeating steps (d)(1)-(d)(5) for each memory cell of said configuration memory cells of the FPGA.

17. A method according to claim 16, wherein each of said third LSSD scan registers includes a selective coupling means programmable, per associated configuration data in an associated memory cell of said configuration memory cells, for selectively propagating a signal between said each third LSSD scan register and its associated programmable interconnect of said programmable interconnects of the FPGA;

and

said step (c)(1) includes loading appropriate configuration data into memory cells of said configuration memory cells as associated with said third LSSD scan registers of the select programmable interconnects, so as to couple said third LSSD scan registers of said select input interconnect scan chain to respective input sides of said first set of interconnects.

18. A method according to claim 17, further comprising repeating steps (c)(1)-(c)(7) a plurality of times employing different associated sets of interconnects with associated select input and output interconnect scan chains for testing the various programmable interconnects of the FPGA.

19. A method according to claim 13, further comprising repeating steps (b)(1)-(b)(7), a plurality of times employing different associated configuration test vectors so as to fully exercise and test the configuration logic.

20. A method of testing a Field Programmable Gate Array, FPGA, said method comprising steps of:

(a) providing an FPGA having;

a plurality of pins;

a plurality of I/O functional signal lines associated with functional pins of said plurality of pins;

a plurality of programmable logic units providing particular logic circuits in accordance with associated logic configuration data;

a plurality of programmable interconnects for selectively interconnecting select I/O functional lines of the I/O functional signal lines and select programmable logic units of the plurality of programmable logic units in accordance with associated routing configuration data;

a plurality of memory cells, designated memory cells of the plurality of memory cells being designated to the plurality of programmable logic units and the plurality of programmable interconnects for retaining the associated logic configuration data and routing configuration data respectively;

configuration logic for accessing particular memory cells of the plurality of memory cells in accordance with memory request signals;

first LSSD scan registers disposed as a boundary scan chain across the I/O functional signal lines;

second LSSD scan registers disposed as a configuration scan chain in association with the configuration logic; and

third LSSD scan registers providing interconnect scan chains disposed along select programmable interconnects of said plurality of programmable interconnects, the third LSSD scan registers being selectively coupled to respective programmable interconnects in accordance with associated latch configuration data as retained in appropriate memory cells of the plurality of memory cells;

(b) testing the various scan chains by;

(1) scanning known test data serially through each of the boundary scan chain, configuration scan chain and interconnect scan chains; and

(2) comparing data scanned through said each scan chain to its associated known test data for determining functionality of said each scan chain;

(c) testing the I/O functional signal lines and associated functional pins by;

(1) passing known test data through the I/O functional signal lines between the associated functional pins and the associated first LSSD scan registers of the boundary scan chain; and

(2) comparing data actually passed therethrough with the known test data for determining functionality of the I/O functional signal lines and the associated functional pins;

(d) testing the configuration logic by;

(1) scanning a test vector serially into the configuration scan chain and applying the test vector to the configuration logic;

(2) latching result data as effected by the configuration logic per the applied test vector, into the configuration scan chain as latched result data;

(3) scanning the latched result data serially out of the configuration scan chain as retrieved data; and

(4) comparing the retrieved data to expected result data, as previously determined in accordance with the test vector and intended operation of the configuration logic, for determining functionality of the configuration logic; and

(e) testing the programmable interconnects by;

(1) configuring a first set of interconnects of the plurality of programmable interconnects, per associated routing configuration data, for propagating data, each interconnect of the first set of interconnects having an input side and an output side;

(2) configuring a first interconnect scan chain of said interconnect scan chains, per associated repeater latch configuration data, for applying data thereof to the input sides of said first set of interconnects;

(3) providing a second interconnect scan chain for receiving data from the output sides of said first set of interconnects;

(4) scanning known test data serially into the first interconnect scan chain and applying the known test data to the input sides of said first set of interconnects;

(5) latching data presented at the output sides of said first set of interconnects into the second interconnect scan chain as latched result data;

(6) scanning data serially out of the second interconnect scan chain and recovering the latched result data as retrieved data; and

(7) comparing the retrieved data to the known test data for determining functionality of the first set of interconnects.

21. A method according to claim 20, further comprising a step (f) of testing said plurality of memory cells by:

(1) writing known input data into given locations of said plurality of memory cells;

(2) reading data from the given locations of said plurality of memory cells; and

(3) comparing the data as read therefrom to the known input data for determining functionality of said memory cells.

22. A method according to claim 21, wherein said step (d) preceeds step (f).

23. A method according to claim 22, wherein said step (e) follows said step (f).