Phase-locked loop oscillator, and moving-average circuit, and division-ratio equalization circuit suitable for use in the same
First Claim
1. A phase-locked loop oscillator comprising:
- means for obtaining a first digital value indicating a mean frequency of an input signal;
means for obtaining a second digital value indicating a mean phase difference of an output signal relative to said input signal;
means for calculating a control value on the basis of said first and said second digital values;
means for selecting a division ratio from two division ratios in accordance with a control signal;
a dual-modulus frequency divider for generating said output signal by frequency-dividing a reference signal, said frequency divider being capable of operating with the division ratio selected;
by said selecting means andfrequency divider control signal generating means for generating said control signal for controlling said dual-modulus frequency divider in accordance with said control value.
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Accused Products
Abstract
In a first phase-locked loop, a digital value corresponding to the mean frequency of an input clock signal is obtained. In a second phase-locked loop, the mean value of the phase difference of an output clock relative to the input clock is measured and is added to the digital value corresponding to the mean frequency, to obtain a control value. From this control value, a control signal for uniformly controlling a dual-modulus frequency divider is generated and supplied to the dual-modulus frequency divider. In a moving-average circuit, a selector selects input data when updating the contents of a serial latch circuit array, and selects an output of the serial latch circuit array when accumulating values. Values serially output from the latch circuit array for accumulation are successively added up using an adder and a latch circuit. In a division-ratio equalization circuit, a calculating circuit calculates quotients a0, a1, a2 . . . am when the control value is expressed as 1/(a0 +1/(a1 +1/(a2 + . . . +1/am)) . . . ), and the quotients are set as division ratios in programmable frequency dividers connected in cascade, through which a reference clock signal is frequency-divided to obtain the control signal.
17 Citations
19 Claims
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1. A phase-locked loop oscillator comprising:
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means for obtaining a first digital value indicating a mean frequency of an input signal; means for obtaining a second digital value indicating a mean phase difference of an output signal relative to said input signal; means for calculating a control value on the basis of said first and said second digital values; means for selecting a division ratio from two division ratios in accordance with a control signal; a dual-modulus frequency divider for generating said output signal by frequency-dividing a reference signal, said frequency divider being capable of operating with the division ratio selected;
by said selecting means andfrequency divider control signal generating means for generating said control signal for controlling said dual-modulus frequency divider in accordance with said control value. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A moving-average circuit comprising;
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a storage circuit for storing a predetermined number of successive numeric values, and for individually and serially outputting all the numeric values stored therein each time the stored contents thereof are updated with entry of a new numeric value; and a single accumulator circuit for successively adding up the numeric values serially output from said storage circuit, said accumulator circuit being cleared when the stored contents of said storage circuit is updated, wherein said storage circuit has; a data holding circuit including a plurality of data latch circuits connected in series, each for latching and outputting an input numeric value, a number of said data latch circuits being equal to said predetermined number of numeric values; and a selector circuit for selecting a new numeric value for input to said data holding circuit when updating the stored contents of said storage circuit, and selecting an output of said data holding circuit for input to said data holding circuit when sequentially outputting the numeric values stored in said storage circuit. - View Dependent Claims (15)
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16. A division-ratio equalization circuit for generating a control signal by which a dual-modulus frequency divider, capable of operating with a division ratio selected from two division ratios in accordance with a control signal and controlled so that the division ratio is equally distributed along the time axis in accordance with an input control value, comprising;
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a calculating circuit that, from the input control value, successively calculates quotients a0, a1, a2 . . . am for output, when said control value is expressed as 1/(a0 +1/(a1 +1/(a2 + . . . +1/am)) . . . ); and a control signal generating circuit that includes a cascaded chain of a plurality of programmable frequency dividers in which said plurality of quotients a0, a1, a2 . . . am are set as respective division ratios, and that frequency-divides a reference signal through the cascaded chain of said plurality of programmable frequency dividers and outputs the result as said control signal. - View Dependent Claims (17, 18, 19)
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Specification