System and method to coherently and dynamically remap an at-risk memory area by simultaneously writing two memory areas

• US 5,867,642 A
• Filed: 08/10/1995
• Issued: 02/02/1999
• Est. Priority Date: 08/10/1995
• Status: Expired due to Term

• Current Assignee: Dell USA LP (Dell Technologies Inc.)
• Original Assignee: Dell USA LP (Dell Technologies Inc.)
• Inventors: Chan, Richard, Vivio, Joseph
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Elmore, Stephen C.
• Application Number:
  US08/512,691
• Time in Patent Office: 1,272 Days
• Field of Search: 395/182.05, 395/182.06, 395/183.18, 395/185.01, 395/185.07, 371/21.1, 371/40.1, 371/40.2, 371/49.1, 364/243, 364/245.3, 364/265, 364/268.5, 364/268.9, 364/269.2, 364/281.9, 364/944, 364/944.2, 364/945
• US Class Current: 714/6.13
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G11C 29/74 using duplex memories, i.e. using dual copies
• CPC Class Codes: G11C 29/765 in solid state disks

Abstract

In a computer system comprising a CPU, main memory, and a memory controller, a system and method to dynamically remap memory while maintaining memory coherency. The main memory is divided into memory areas, one of which is a reserve memory area. Memory accesses are checked for errors and the errors are logged, as is the memory area in which the error occurred. The error log for each memory area is compared to an acceptable error frequency level. If a particular memory area exceeds the acceptable error frequency level, the memory area will be dynamically remapped to the reserve memory area while memory coherency is maintained. The dynamic remapping is performed by copying the memory from the memory area which exceeded the acceptable error frequency level, to the reserve memory are. During the copying, all writes to the memory area which exceeded the acceptable error frequency level are concurrently performed to both the memory area which exceeded the acceptable error frequency level and to the reserve memory area, thus preserving memory coherency. Also, the copying is performed in small blocks to avoid system timing problems.

Claims

1. In a computer system comprising a central processing unit (CPU), a memory controller coupled to the CPU, and a memory coupled to the memory controller, wherein the memory is divided into areas, wherein the CPU performs read and write accesses of the memory through the memory controller, the computer system further comprising at least one other device performing write accesses of the memory through the memory controller, a method for dynamically remapping an at risk memory area to a reserve memory area, the method comprising:

determining if one of said memory areas is at risk for failure;

concurrently performing all write accesses of said at risk memory area to both said at risk memory area and to said reserve memory area, wherein said concurrently performing all write accesses is performed in response to determining that one of said memory areas is at risk for failure;

copying said at risk memory area to said reserve memory area, wherein said copying is performed in response to determining that one of said memory areas is at risk for failure;

wherein said concurrently performing all write accesses continues until said copying is completed and wherein memory coherency is maintained during said copying; and

upon completion of said copying, mapping all accesses which were previously mapped to said at risk memory area, to said reserve memory area only, wherein said at risk memory area is no longer accessed.

2. The method of claim 1, wherein said determining if one of said memory areas is at risk comprises:

determining an error frequency level that indicates one of said memory areas is at risk for failure;

detecting if an error occurs whenever said memory areas are accessed;

tracking the frequency of said errors detected in each one of said memory areas; and

for each one of said memory areas, comparing said frequency of said errors detected in each one of said memory areas to said error frequency level and thereby determining if one of said memory areas is at risk for failure.

3. The method of claim 2, wherein said detecting comprises using error correction codes stored in said memory to detect errors without halting system operation.

4. The method of claim 2, wherein said tracking comprises:

interrupting said CPU when one of said errors is detected for said one of said memory areas; and

logging the occurrence of said one of said errors for said one of said memory areas, wherein said logging is performed, in response to said interrupting, by a system management computer program executed by said CPU.

5. The method of claim 2, wherein said comparing is performed by a system management computer program executed by said CPU.

6. The method of claim 1, wherein said memory controller asserts a row address strobe (RAS) for one of said memory areas when said one of said memory areas is accessed;

and

wherein said concurrently performing all write accesses of said at risk memory area comprises programming said memory controller to concurrently assert both the row address strobe for said at risk memory area and the row address strobe for said reserve memory area during said write accesses.

7. The method of claim 6, wherein said programming said memory controller to assert both the row address strobe for said at risk memory area and the row address strobe for said reserve memory area during said write accesses is performed by a system management computer program executed by said CPU.

8. The method of claim 1, wherein said computer system farther comprises devices and applications that require frequent accesses to said memory;

wherein said copying is performed by a system management computer program executed by said CPU; and

wherein said copying is performed in small blocks, wherein said copying of each of said blocks is performed in a relatively small amount of time so that said copying does not prevent said devices and applications that require frequent accesses to said memory from accessing said memory for an extended amount of time.

9. The method of claim 1, wherein said mapping all accesses which were previously mapped to said at risk memory area to said reserve memory area only is performed by a system management computer program executed by said CPU.

10. The method of claim 1, wherein each of said memory areas comprise a single in-line memory module, the method further comprising generating a message identifying the single in-line memory module associated with said at risk memory area and recommending replacement of said single in-line memory module.

11. The method of claim 1 further comprising selecting between a first mode and a second mode, wherein when said first mode is selected, said determining, said performing, said copying, and said programming are performed;

but when said second mode is selected, said determining, said performing, said copying, and said programing are not performed and said reserve memory area is used as a normal memory area, thereby increasing the total amount of memory available.

12. A system for coherent, dynamic remapping of memory in a computer system from an at risk memory area to a reserve memory area, comprising:

a central processing unit (CPU);

a memory controller coupled to said CPU and comprising error detection and correction logic, concurrent write logic, and mapping logic;

memory, coupled to said memory controller, physically divided into areas, wherein one of said memory areas is a reserve memory area used for remapping of at risk memory, and wherein said CPU performs read and write accesses of said memory through said memory controller; and

a bus master device which performs write accesses of said memory through said memory controller;

wherein said error detection and correction logic detects if an error occurs when each of said memory areas is accessed and stores error information associated with each of said memory areas;

wherein one of said memory areas is copied to said reserve memory area in response to said error detection and correction logic detecting a first number of errors in one of said memory areas;

wherein said concurrent write logic operates in response to said error detection and correction logic detecting said first number of errors in one of said memory areas to concurrently perform all write accesses directed to said one of said memory areas to both said one of said memory areas and to said reserve memory area;

wherein memory coherency is maintained when said one of said memory areas is copied to said reserve memory area; and

wherein said mapping logic operates in response to said detection and correction logic detecting said first number of errors in one of said memory areas to change mapping of said read and write accesses from one of said memory areas to said reserve memory area.

13. The system of claim 12 wherein each of said memory areas comprises a single in-line memory module.

14. The system of claim 12 wherein each of said memory areas comprises error correction codes used by said error detection and correction logic to correct simple errors in said memory areas without halting system operation.

15. The system of claim 12, wherein each of said memory areas has an associated row address strobe (RAS), and wherein said concurrent write logic performs said concurrently performed writes by concurrently asserting both the row address strobe for said one of said memory areas and the row address strobe for said reserve memory area during said write accesses.

16. The system of claim 12, further comprising a plurality of subcontrollers which include:

a subcontroller configured to determine if one of said memory areas is at risk based upon said error information stored by said error detection and correction logic;

a subcontroller configured to operate said concurrent write logic to concurrently perform all writes directed to said at risk memory area, to both said at risk memory area and to said reserve memory area;

a subcontroller configured to copy said at risk memory area to said reserve memory area; and

a subcontroller configured to operate said mapping logic to map said read and write accesses previously mapped to said at risk memory area to said reserve memory area.

17. The system of claim 16, wherein said subcontroller configured to copy said at risk memory area to said reserve memory area is further configured to copy said at risk memory area to said reserve memory area in small blocks, wherein each of said blocks is copied in a relatively short amount of time so that devices and applications that require frequent access to said memory are not prevented from accessing said memory for an extended amount of time.

18. The system of claim 17, wherein said subcontroller configured to determine if one of said memory areas is at risk comprises:

a subcontroller configured to determine an error frequency level that indicates one of said memory areas is at risk for failure;

a subcontroller configured to retrieve said error information from said error detection and correction logic each time said errors occur;

a subcontroller configured to track the frequency of said errors detected in each one of said memory areas; and

a subcontroller configured to compare said frequency to said error frequency level for said each one of said memory areas, and thereby determining if one of said memory areas is at risk.

19. The system of claim 18, wherein at least one of said plurality of subcontrollers comprises a computer program executed on said CPU.

20. The system of claim 18, wherein said system further comprises a system management controller coupled to said memory controller, and wherein at least one of said plurality of subcontrollers comprises a computer program executed on said system management controller.

21. The system of claim 18, wherein at least one of said plurality of subcontrollers comprises circuitry within said memory controller.

22. The system of claim 12, further comprising:

means for determining if one of said memory areas is at risk based upon said error information stored by said error detection and correction logic;

means for operating said concurrent write logic to concurrently perform all writes directed to said at risk memory area, to both said at risk memory area and to said reserve memory area;

means for operating said CPU to copy said at risk memory area to said reserve memory area; and

means for operating said mapping logic to map said read and write accesses previously mapped to said at risk memory area to said reserve memory area.

23. The system of claim 22, wherein said computer system comprises devices and applications that require frequent accesses to said memory;

and wherein said means for operating said CPU to copy said at risk memory area to said reserve memory area is further configured to operate said CPU to copy said at risk memory area to said reserve memory area in small blocks, wherein each of said blocks is copied in a relatively short amount of time so that said devices and applications that require frequent access to said memory are not prevented from accessing said memory for an extended amount of time.

24. The system of claim 23, wherein said means for determining if one of said memory areas is at risk comprises:

means for determining an error frequency level that indicates one of said memory areas is at risk for failure;

means for retrieving said error information from said error detection and correction logic each time said errors occur;

means for tracking the frequency of said errors detected in each one of said memory areas; and

means for comparing said frequency to said error frequency level for said each one of said memory areas, and thereby performing said determining if one of said memory areas is at risk.

25. The system of claim 24, wherein each said means comprises a computer program executed on said CPU.

26. The system of claim 12, wherein said CPU determines if one of said memory areas is at risk based upon said error information stored by said error detection and correction logic;

wherein said CPU operates said concurrent write logic to concurrently perform all writes directed to said at risk memory area, to both said at risk memory area and to said reserve memory area;

wherein said CPU copies said at risk memory area to said reserve memory area; and

wherein said CPU operates said mapping logic to map said read and write accesses previously mapped to said at risk memory area to said reserve memory area.

27. The system of claim 26, wherein said CPU copies said at risk memory area to said reserve memory area in small blocks, wherein said CPU copies each of said blocks in a relatively short amount of time so that said devices and applications that require frequent access to said memory are not prevented from accessing said memory for an extended amount of time.

28. The system of claim 27, wherein said CPU determines an error frequency level that indicates one of said memory areas is at risk for failure;

wherein said CPU retrieves said error information from said error detection and correction logic each time said errors occur;

wherein said CPU tracks the frequency of said errors detected in each one of said memory areas; and

wherein said CPU compares said frequency to said error frequency level for said each one of said memory areas, and thereby performing said determining if one of said memory areas is at risk.

29. A memory controller for a computer system comprising a central processing unit (CPU) and memory areas, wherein the CPU performs read and write accesses of the memory areas through the memory controller, the memory controller comprising:

error detection and correction logic for detecting if an error occurs when each of said memory areas is accessed, and for storing error information associated with each of said memory areas;

wherein said CPU copies one of said memory areas to a reserve memory area in response to said detection and correction logic detecting a first number of errors in one of said memory areas;

concurrent write logic for concurrently performing all write accesses directed to one OF said memory areas to both said one of said memory areas and to said reserve memory area in response to said detection and correction logic detecting said first number of errors in one of said memory areas, wherein memory coherency is maintained when said CPU copies one of said memory areas to said reserve memory area; and

mapping logic for mapping of read and write accesses to said memory areas, wherein said mapping logic changes mapping of said read and write accesses from one of said memory areas to said reserve memory area in response to said detection and correction logic detecting said first number of errors in one of said memory areas.