Synchronizing system between function blocks arranged in hierarchical structures and large scale integrated circuit using the same

• US 5,867,691 A
• Filed: 03/15/1993
• Issued: 02/02/1999
• Est. Priority Date: 03/13/1992
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Shiraishi, Hajime
• Primary Examiner(s): TOPLU, LUCIEN
• Application Number:
  US08/031,363
• Time in Patent Office: 2,150 Days
• Field of Search: 395/550, 395/325, 395/551, 395/555, 364/488, 364/489
• US Class Current: 713/400
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 30/35 Delay-insensitive circuit design, e.g. asynchronous or self-timed
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

An inter-hierarchy synchronizing system and an LSI include a plurality of function blocks taking a hierarchical structure and having timing systems expressed by timing variables independent of each other and inter-hierarchy synchronizing blocks disposed these hierarchies. This synchronizing block has: an input event temporary storage part for receiving and storing an input event generation signal group from a higher-level block; an activation timing judging part for judging activations of a plurality of function blocks and transmitting activation signals; an output event temporary storage part for receiving and storing output event generation signals including a completion signal from lower-level blocks; and a final completion signal judging part for judging a final completion state on the basis of a signal from the output event temporary storage part and transmitting a final completion signal to the high-block. The pre-designed function blocks are operable at a high speed without undergoing an influence by a delay of clocks.

Claims

1. An inter-hierarchy synchronizing system comprising:

a higher-level functional hardware block for generating input event generation signals in accordance with a timing relation in a higher-level timing system in which timings are expressed by higher-level timing variables;

a lower-level functional hardware block, arranged in a hierarchical structure in combination with said higher-level functional hardware block, for performing predetermined operations in accordance with a local timing relation in a local timing system in which timings are expressed by a local timing variable that is not necessarily coincident with said higher-level timing variables on the basis of activation signals, wherein requirements of said system are functionally decomposed into said lower-level and higher-level functional hardware blocks; and

an inter-hierarchy synchronizing means, provided between said higher-level functional hardware block and said lower-level functional hardware block, for outputting said activation signals for activating said lower-level functional hardware block by said local timing system on the basis of said input event generation signals generated by said higher-level functional hardware block, supplying said activation signals to said lower-level functional hardware block, generating a task completion signal at said higher-level timing system when an output event generation signal generated from said lower-level functional hardware block is set to indicate that all tasks are completed by said lower-level functional hardware block, and supplying said task completion signal to said higher-level functional hardware block,

wherein said system is arranged in a hierarchical structure in which said higher-level functional hardware block controls a plurality of lower-level functional hardware blocks each having a local timing system, and said inter-hierarchy synchronizing means activates said plurality of lower-level functional hardware blocks in parallel.

2. The inter-hierarchy synchronizing system according to claim 1, wherein said inter-hierarchy synchronizing means includes a judging means for receiving task completion signals from said plurality of lower-level functional hardware blocks and generating said task completion signal when task completion signals from all of lower-level functional hardware blocks have been received.

3. The inter-hierarchy synchronizing system according to claim 2, wherein said inter-hierarchy synchronizing means assigns and sets estimation of timings which are determined according to a system requirement specification by said higher-level functional hardware block when the timings of signals defined in said lower-level functional hardware blocks and in said higher-level functional hardware block are used, and said lower-level functional hardware blocks report to said higher-level functional hardware block time interval variables expressed as a relationship between the estimation of timings and the timings defined in said lower-level functional hardware blocks and in said higher-level functional hardware block.

4. The inter-hierarchy synchronizing system according to claim 3, wherein a time interval variable is expressed as any one of a before-and-after relationship, a simultaneous relationship, a time in-and-out relationship and an unrelated relationship.

5. The inter-hierarchy synchronizing system according to claim 1, wherein at least any one of said higher-level functional hardware blocks and said lower-level functional hardware block has already been designed and library-registered.

6. The inter-hierarchy synchronizing system according to claim 1, wherein functions of said inter-hierarchy synchronizing means are realized by a timing simulation which is a simulation of timings with mutual relations and real timing simulation after an automatic logic synthesis by use of respective timing variables of said lower-level functional hardware block and said higher-level functional hardware block.