Dynamic system clocking and address decode circuits, methods and systems

• US 5,867,717 A
• Filed: 05/16/1997
• Issued: 02/02/1999
• Est. Priority Date: 12/22/1994
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Milhaupt, Robert W., Bridgewater, James
• Primary Examiner(s): Donaghue, Larry D.
• Assistant Examiner(s): FOLLANSBEE, JOHN A
• Application Number:
  US08/857,396
• Time in Patent Office: 627 Days
• Field of Search: 395/750.01, 395/750.04, 395/750.05, 395/750.06, 395/800.32, 395/800.36
• US Class Current: 713/323
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3265 Power saving in display device
• CPC Class Codes: G06F 13/124 where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
• CPC Class Codes: G06F 2213/0038 System on Chip
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A single-chip integrated circuit device (110) includes an on-chip bus (904) and a plurality of integrated circuit functional blocks (934, 932) having respective clock inputs connected to the on-chip bus (904). An address decoder (in 1210) is provided responsive to particular addresses to supply an output of a differing character (IDE/NON-IDE) depending on whether or not the particular addresses are received. A clock generating circuit (1201) having a control input (IDE/NON-IDE) fed by the output of the address decoder (in 1210) and a clock output (SYSCLK) connected to the on-chip bus (904) supplies a clock signal that depends in rate on whether or not the particular addresses are received. Other circuits, systems, and methods are disclosed.

Claims

1. A computer system comprising:

a microprocessor having a clock output and an address output; and

a peripheral processor unit including;

an on-chip bus coupled to receive addresses from said microprocessor;

a plurality of peripheral controllers having respective clock inputs connected to said on-chip bus;

an address decoder responsive to particular said addresses, said particular addresses indicative of at least one of said peripheral controller, to supply an output of a differing character depending on whether or not the particular addresses are received; and

a clock generating circuit having a control input coupled to said output of said address decoder and a clock output coupled to the on-chip bus to supply a clock signal for at least one of said peripheral controllers that depends in rate on whether or not the particular addresses are received.

2. The computer system claimed in claim 1 wherein said clock signal that depends in rate is supplied via said on-chip bus to a peripheral controller at an address to which said address decoder is responsive.

3. The computer system claimed in claim 1 further comprising a register coupled to said clock generating circuit having a plurality of bits for programming the operation of said clock generating circuit.

4. The computer system claimed in claim 3 wherein said bits comprise at least one bit that indicates the clock rate of an external clock input to said clock generating circuit from said microprocessor.

5. The computer system claimed in claim 3 further comprising a PCI-to-ISA bus interface circuit having external terminals for a PCI bus and internally coupled to said on-chip bus, said at least one bit indicating the PCI clock rate.

6. The computer system claimed in claim 3 wherein said bits comprise at least one bit indicative of the clock rate at which to run at least one particular peripheral controllers of said plurality of said peripheral controllers.

7. The computer system claimed in claim 6 wherein said particular peripheral controller is a hard-disk interface.

8. The computer system claimed in claim 6 wherein said bits comprise at least one bit indicative of the clock rate at which to run at least one other peripheral controller of said plurality of peripheral controllers other than said particular peripheral controller.

9. The computer system claimed in claim 8 wherein said other peripheral controller is responsive to non-hard-disk accesses.

10. A personal computer comprising:

an input device;

a memory;

a display;

a microprocessor coupled to said input device, said memory, and said display; and

an integrated circuit coupled to said microprocessor comprising;

a bus coupled to receive addresses from said microprocessor;

a plurality of peripheral controllers having respective clock inputs connected to said bus;

an address decoder responsive to particular addresses, said particular addresses indicative of at least one of said peripheral controllers, to supply an output of a differing character depending on whether or not the particular addresses are received; and

a clock generating circuit having a control input coupled to said output of said address decoder and a clock output coupled to said bus to supply a clock signal that depends in rate on whether or not the particular addresses are received.

11. The personal computer claimed in claim 10 further comprising a register coupled to said clock generating circuit having a plurality of bits for programming the operation of said clock generating circuit.

12. The personal computer claimed in claim 11 wherein said bits comprise at least one bit that indicates the clock rate of an external clock input to said clock generating circuit.

13. The personal computer claimed in claim 12 further comprising a PCI-to-ISA bus interface circuit having external terminals for a PCI bus and internally coupled to said bus, said at least one bit indicating the PCI clock rate.

14. The personal computer claimed in claim 11 wherein said bits comprise at least one bit indicative of the clock rate at which to run at least one particular peripheral controller of said plurality of peripheral controllers.

15. The personal computer claimed in claim 14 wherein said particular peripheral controller is a hard-disk interface.

16. The personal computer claimed in claim 14 wherein said bits comprise at least one bit indicative of the clock rate at which to run at least one other peripheral controller of said plurality of said peripheral controllers other than said particular functional block.

17. The personal computer claimed in claim 16 wherein said other peripheral controller is responsive to non-hard-disk accesses.

18. The personal computer claimed in claim 10 wherein said clock signal that depends in rate is supplied via said bus to a peripheral controller at an address to which said address decoder is responsive.

19. The personal computer claimed in claim 10 wherein said clock generating circuit comprises a programmable clock divider.

20. The personal computer claimed in claim 10 wherein said input device includes a keyboard.

21. The personal computer claimed in claim 10 wherein said display includes a CRT.

22. The personal computer claimed in claim 10 wherein the personal computer has the form of a notebook computer.

23. A personal computer comprising:

provision for user input;

a memory;

provision for output;

a microprocessor coupled to said provision for user input, to said memory and to said provision for output; and

an integrated circuit coupled to said microprocessor comprising;

a bus coupled to receive addresses from said microprocessor;

a plurality of peripheral controller having respective clock inputs connected to said bus;

an address decoder responsive to particular addresses, said particular addresses indicative of at least one of said peripheral controllers to supply an output of a differing character depending on whether or not the particular addresses are received; and

a clock generating circuit having a control input coupled to said output of said address decoder and a clock output coupled to said bus to supply a clock signal that depends in rate on whether or not the particular addresses are received.

24. A personal computer as claimed in claim 23 wherein said provision for user input comprises an input connector.

25. A personal computer as claimed in claim 24 further comprising an input device connected to said input connector.

26. A personal computer as claimed in claim 25 further comprising a display connected to said output connector.

27. A personal computer as claimed in claim 23 wherein said provision for output comprises an output connector.