System for data transfer across asynchronous interface

• US 5,867,731 A
• Filed: 08/12/1996
• Issued: 02/02/1999
• Est. Priority Date: 08/12/1996
• Status: Expired due to Term

• Current Assignee: Unisys Corporation
• Original Assignee: Unisys Corporation
• Inventors: Williams, David P., Sutter, Stephen
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): ELISCA, PIERRE E
• Application Number:
  US08/695,618
• Time in Patent Office: 904 Days
• Field of Search: 395/849, 395/824, 395/734, 395/393, 395/733, 395/487, 395/183.04, 395/183.06, 395/183.21, 395/500, 395/200.7
• US Class Current: 710/29
• CPC Class Codes: H04L 12/46 Interconnection of networks

Abstract

A system for use in transferring data packets across different clock domains using an input data register for receiving a block of data packets with the input data register and a plurality of interface registers located in the first clock domain for transferring a block of data packets from the input register to a second clock domain in response to a request signal with the system prioritizing the transfer of multiple data packets within the block of data packets by length in order to transfer the longer word packets first and the shorter word packets last with the shortest word packets within the block bundled together and simultaneously transferring across an asynchronous interface.

Claims

1. A system for use in transferring data packets across different clock domains comprising:

an integrated logic chip;

an input data register in the logic chip for receiving a data packet with the input data register located in a first clock domain;

a first control logic in said chip for taking a snapshot of a block of data packets to be transferred to the input data register;

a second control logic for prioritizing the data packets in the block of data packets according to length; and

a plurality of interface registers located in the first clock domain for transferring two or more data packets in the block of data packets from the input register to a second clock domain during a single transfer cycle.

2. The system of claim 1 including at least three interface registers.

3. The system of claim 2 wherein the interface registers are two words wide.

4. The system of claim 1 including a plurality of staging registers for transferring the data packets to the interface registers.

5. The system of claim 4 including a multiplexer for directing the data packets into the staging registers.

6. The system of claim 5 wherein the system transfers the longest data packets within the group of data packets before the shorter data packets are transferred.

7. The system of claim 5 wherein the interface registers simultaneously transfers the data packets of two words in length within the group of data packets into the second clock domain.

8. The method of transferring data packets across an asynchronous interface comprising:

taking a snapshot of data packets to select a block of data packets to be transferred from one clock domain to another clock domain; and

prioritizing the transfer of data packets within the block of data packets by length and transferring the longer data packets across the asynchronous interface before transferring the shorter data packets and then simultaneously transferring the shortest data packet within the block of data packets across the asynchronous interface.

9. The method of claim 8 including the transfer of data packets ranging from two words to ten words in length.

10. A system for use in transferring data packets of various sizes between a plurality of input/output processors and an uplink without the use of a buffer and without causing a backup of the data packets where the rate of transfer of data to the input/output processors is less than the rate of transfer of data to the uplink comprising:

an integrated logic chip;

a first control logic in said chip;

a bus for sending data packets to the logic chip;

an input data register in the logic chip for receiving or transferring two word data packets at a time;

a plurality of input/output processors connected to said bus for sending data packets of up to 10 words to said input data register;

a first staging register for receiving two-word data packets from said input data register;

a second staging register for receiving two-word data packets from said input data register;

a third staging register for receiving two-word data packets from said input data register;

a first interface register for uplinking two-word data packets from said first staging register in response to a request signal from the control logic;

a second interface register for uplinking two-word data packets from said second staging register in response to a request;

a third interlace register for uplinking two-word data packets from said third staging register in response to a request signal from the control logic, whereby any two data packets in any of the interface register are simultaneously uplinked.