Method for storing prioritized memory or I/O transactions in queues having one priority level less without changing the priority when space available in the corresponding queues exceed

• US 5,867,735 A
• Filed: 02/09/1998
• Issued: 02/02/1999
• Est. Priority Date: 06/07/1995
• Status: Expired due to Term

• Current Assignee: Microunity Systems Engineering Incorporated
• Original Assignee: Microunity Systems Engineering Incorporated
• Inventors: Robinson, Timothy, Zuravleff, William K., Semmelmeyer, Mark, Furman, Scott
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Perveen, Rehana
• Application Number:
  US09/020,859
• Time in Patent Office: 358 Days
• Field of Search: 395/826, 395/677, 395/651, 395/673, 395/671, 395/825, 395/856, 395/872, 395/874, 370/54
• US Class Current: 710/52
• CPC Class Codes: G06F 9/3824 Operand accessing

Abstract

A non-blocking load buffer is provided for use in a high-speed microprocessor and memory system. The non-blocking load buffer interfaces a high-speed processor/cache bus, which connects a processor and a cache to the non-blocking load buffer, with a lower speed peripheral bus, which connects to peripheral devices. The non-blocking load buffer allows data to be retrieved from relatively low bandwidth peripheral devices directly from programmed I/O of the processor at the maximum rate of the peripherals so that the data may be processed and stored without unnecessarily idling the processor. I/O requests from several processors within a multiprocessor may simultaneously be buffered so that a plurality of non-blocking loads may be processed during the latency period of the device. As a result, a continuous maximum throughput from multiple I/O devices by the programmed I/O of the processor is achieved and the time required for completing tasks and processing data may be reduced. Also, a multiple priority non-blocking load buffer is provided for serving a multiprocessor running real-time processes of varying deadlines by prioritization-based scheduling of memory and peripheral accesses.

Claims

1. A method for limiting admission of prioritized memory or I/O transactions for storage in a memory comprising:

(a) dividing the memory into a plurality of queues having unique priority levels;

(b) channeling said prioritized memory or I/O transactions to the ones of said queues having its unique priority level corresponding to said prioritized memory or I/O transactions;

(c) storing said prioritized memory or I/O transactions in the corresponding queues when space is available therein; and

(d) storing said prioritized memory or I/O transactions in one of said queues having a priority level which is one priority level less than the unique priority level corresponding to said prioritized memory or I/O transactions channeled at said step (b), without changing the priority of said prioritized memory or I/O transactions, when the space available in the queues corresponding to said prioritized memory or I/O transactions is exceeded, wherein said plurality of queues provides for the execution of prioritized memory or I/O transactions on a non-FIFO basis and order of priority.

2. A method according to claim 1, wherein the memory is contained within a non-blocking load buffer.

3. A method according to claim 1, wherein said memory or I/O transactions comprise loads and stores.

4. A method according to claim 1, further comprising the step of specifying a maximum number of outstanding memory or I/O transactions for said unique priority levels.

5. A method according to claim 1, further comprising the step of determining priorities corresponding to entries of memory or I/O transactions by logical memory addresses, control bits derived from a memory management page table, control bits derived from segmentation entries, virtual addresses of a memory management system, programmable registers which set priorities for each processor, instructions, or instruction operands.