Modular panel stacking process

• US 5,869,353 A
• Filed: 11/17/1997
• Issued: 02/09/1999
• Est. Priority Date: 11/17/1997
• Status: Expired due to Term

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Dense-Pac Microsystems Incorporated
• Inventors: Levy, Aaron Uri, Sprint, John Patrick, Forthun, John Arthur, Isaak, Harlan Ruben, Mearig, Joel Andrew, Calkins, Mark Chandler
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Jones, Josetta I.
• Application Number:
  US08/971,499
• Time in Patent Office: 449 Days
• Field of Search: 438/113, 438/111, 438/110, 438/109, 438/366, 438/368
• US Class Current: 438/109
• CPC Class Codes: H01L 2225/1005 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2225/1029 the support being a lead frame
• CPC Class Codes: H01L 2225/107 Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB printed circuits H05K1/00
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H05K 1/144 Stacked arrangements of planar printed circuit boards
• CPC Class Codes: H05K 1/182 associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]

Abstract

A method of making chip stacks begins with the formation of a plurality of panels having apertures therein and conductive pads on opposite sides thereof. Solder paste is deposited on the conductive pads prior to mounting plastic packaged IC chips within each of the apertures in each of the panels so that opposite leads thereof reside on the conductive pads at opposite sides of the apertures. The plural panels are then assembled into a stack, such as by use of a tooling jig which aligns the various panels and holds them together in compressed fashion. The assembled panel stack is heated so that the solder paste solders the leads of the packaged chips to the conductive pads and interfacing conductive pads of adjacent panels together, to form a panel stack comprised of a plurality of chip package stacks. Following cleaning of the panel stack to remove solder flux residue, the individual chip package stacks are separated from the panel stack by cutting and breaking the stack. Score lines across a topmost panel and transverse slots within remaining panels therebelow result in the formation of strips of chip package stacks when longitudinal cuts are made through the panel stack. The remaining portions of the uppermost panel within such strips are then snapped along the score lines thereof to separate the individual chip package stacks from the strips.

Claims

1. A method of making chip stacks comprising the steps of:

providing a plurality of panels, each having a plurality of apertures therein and a plurality of conductive pads thereon;

providing a plurality of packaged chips having leads extending therefrom;

mounting the plurality of packaged chips within the plurality of apertures in the plurality of panels so that the leads thereof are disposed on at least some of the plurality of conductive pads on the plurality of panels;

assembling the plurality of panels into a panel stack;

soldering the leads of the packaged chips to at least some of the plurality of conductive pads and at least some of the conductive pads on adjacent panels together to form chip package stacks within the panel stack; and

separating the individual chip package stacks from the panel stack;

wherein one of the plurality of panels is scored to facilitate breaking of the panel between adjacent chip package stacks, and the remaining ones of the plurality of panels have elongated slots therein to facilitate separation of adjacent chip package stacks; and

wherein said one of the plurality of panels is scored along a plurality of spaced-apart, parallel score lines which are perpendicular to the elongated slots in said remaining ones of the plurality of panels, and the step of separating the individual chip package stacks includes the steps of cutting through the panel stack along a plurality of spaced-apart, parallel lines which are perpendicular to the score lines, to form a plurality of strips of the chip package stacks, and within each strip breaking the strip along the score lines of a portion of said one of the plurality of panels within the strip to separate the individual chip package stacks from the strip.

2. A method of making chip stacks comprising the steps of:

providing a plurality of thin, planar panels, each having a plurality of apertures therein, a plurality of conductive pads on opposite surfaces of the panel adjacent each of the plurality of apertures, and a plurality of slots therein on opposite sides of each of the plurality of apertures;

mounting a different one of a plurality of packaged chips having leads within each of the plurality of apertures of each of the plurality of panels;

assembling the plurality of panels into a panel stack;

bonding the leads of the plurality of packaged chips to at least some of the plurality of conductive pads of the panels on which the packaged chips are mounted, and bonding at least some of the plurality of conductive pads of each panel to at least some of the conductive pads on at least one adjacent panel of the plurality of panels to form chip package stacks within the panel stack; and

cutting through each of the plurality of panels within the panel stack along lines perpendicular to the plurality of slots in each of the panels to separate the chip package stacks from the panel stack.

3. The method set forth in claim 2, wherein one of the plurality of thin, planar panels is formed without the pluralit of slots therein and is broken following the cutting step to separate the chip package stacks.

4. The method set forth in claim 2, wherein the plurality of apertures in each panel are arranged into columns thereof extending along a length of the panel and rows thereof extending across a width of the panel and the plurality of slots in the panel are located between adjacent rows of the apertures.

5. The method set forth in claim 4, wherein the step of cutting is performed by cutting through each panel of the panel stack along the length of the panel adjacent opposite sides of the columns of apertures.

6. The method set forth in claim 2, wherein each of the plurality of apertures in each of the panels is of rectangular configuration so as to have four side edges which are surrounded by the conductive pads on each of the opposite sides of the panel, and each of the packaged chips comprises a thin, small outline chip package of rectangular configuration having plural leads extending from a pair of opposite side edges of the package and onto the conductive pads adjacent an opposite pair of side edges of an aperture in which the chip package is mounted, the chip package having a thickness like a thickness of the panel between opposite sides of the panel.