Method to form mosfet with an inverse T-shaped air-gap gate structure

• US 5,869,374 A
• Filed: 04/22/1998
• Issued: 02/09/1999
• Est. Priority Date: 04/22/1998
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Texas Instruments Acer Inc (Acer, Inc.)
• Inventors: Wu, Shye-Lin
• Primary Examiner(s): Booth, Richard A.
• Application Number:
  US09/064,262
• Time in Patent Office: 293 Days
• Field of Search: 438/291, 438/305, 438/307, 438/303, 438/592, 438/289
• US Class Current: 438/291
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/4991 comprising an air gap
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66583 with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
• CPC Class Codes: H01L 29/7836 with a significant overlap between the lightly doped extension and the gate electrode H01L29/7834, H01L29/7835 take precedence

Abstract

A method for fabricating a MOS transistor with an inverse T-shaped air-gap gate structure on a semiconductor substrate is disclosed. The T-shaped air-gap gate structure reduces the parasitic resistance and capacitance; hence device structure operation speed can be improved. The method comprises the following steps: firstly, a gate hollow is defined in the pad oxide/nitride layer. Next an ultra-thin nitrogen rich dielectric as a gate oxide is formed. After that, a thin α-Si is deposited, then an ion implantation is done to form a punchthrough stopping region. After forming a CVD oxide film, an anisotropic etching is followed to form oxide spacers. An undoped silicon layer then followed to refill the gate hollow region. A CMP processes or a dry etching is done to remove silicon layer until the nitride layer is exposed. Subsequently, the oxide spacers is removed to expose a dual hollow. A LDD implantation is then implanted into the substrate. Next a pad nitride/oxide layer is successive removed to expose the substrate by a dry etching method. Subsequently, a source/drain/gate implantation and a hight temperature oxidation are carried out to grow an oxide layer and seal the dual hollow so as to form a dual air gap. At the same time the extended S/D junction are formed.

Claims

1. A method for fabricating a MOS transistor with an inverse T-shaped air-gap gate structure on a semiconductor substrate which has a plurality of isolation regions and a pad oxide layer on an active region of said semiconductor substrate, said method comprising the steps of:

forming a nitride layer on said pad oxide layer and said isolation regions;

removing a portion of said nitride layer and said pad oxide layer, thereby leaving a remaining portion of said pad oxide layer to define a gate hollow region;

forming a dielectric layer on said gate hollow;

forming a first silicon layer over all areas of said semiconductor substrate;

performing a first ion implantation into said semiconductor substrate so as to form a punchthrough stopping region in said semiconductor substrate, wherein said region is beneath said dielectric layer;

forming an oxide layer over all surfaces of said semiconductor substrate;

performing an anisotropic etching to etch said oxide layer to form oxide spacers on inner sidewalls of said gate hollow and leave a remaining portion of said gate hollow;

forming a second silicon layer over all areas of said semiconductor substrate to fill said remaining portion of said gate hollow;

removing said oxide spacers on sidewalls of said gate hollow so that a dual hollow is formed;

etching back said second and first silicon layer until said nitride layer is exposed and a flat surface is formed;

performing a second ion implantation so as to form LDD regions in the semiconductor substrate, wherein said regions are formed under a bottom portion of said dual hollow;

removing said nitride layer on said pad oxide layer of said semiconductor substrate;

removing said remaining portion of said pad oxide on said active region of said semiconductor substrate;

performing a third ion implantation to form doped source/drain/gate regions; and

performing a thermal oxidation so as to form an oxide layer on all exposed surfaces and to form air gap structures in sidewalls of said gate structure as well as to form an extended source/drain junction.

2. The method of claim 1, wherein said nitride layer is deposited by LPCVD to a thickness of about 80-300 nm.

3. The method of claim 1, wherein said dielectric layer is a nitrogen-rich oxide with a thickness of about 2-20 nm, and said nitrogen rich oxide is formed in an ambient selected from a group consisting of N₂ O/NO, O₂ :

N₂ =1;

99 and O₂ ;

N₂ =2;

98.

4. The method of claim 1, wherein said first silicon layer is an amorphous silicon and is formed at a temperature of about 350°

-560°

C. to about 10-50 nm by a method selected from a group consisting of PECVD and LPCVD.

5. The method of claim 1, wherein said first ion implantation is implanted by using p-type ions for NMOS transistor with an energy and a dosage of about 30-150 keV and of about 5×

10¹¹ to 5×

10¹³ /cm², respectively.

6. The method of claim 1 wherein said first ion implantation is implanted by using n-type ions for PMOS transistor with an energy and a dosage of about 30-150 keV and of about 5×

10¹¹ to 5×

10¹³ /cm², respectively.

7. The method of claim 1, wherein said oxide layer is deposited to a thickness of about 20-100 nm by a method selected from a group consisting of LPCVD, ECRCVD and PECVD.

8. The method of claim 1, wherein said second silicon layer is amorphous silicon formed by a PECVD method at a temperature of about 250°

-400°

C.

9. The method of claim 1, wherein said second silicon layer is an amorphous silicon layer formed by a LPCVD method at a temperature of about 400°

-550°

C.

10. The method of claim 1, wherein said flat surface is achieved by chemical/mechanical polishing.

11. The method of claim 1, wherein said flat surface is achieved by a dry etching method.

12. The method of claim 1, wherein said second ion implantation is implanted by using n-type ions with an energy and a dosage of about 10-80 keV and of about 5×

10¹² to 2×

10¹⁴ /cm², respectively.

13. The method of claim 1, wherein said second ion implantation is implanted by using p-type ions with an energy and a dosage of about 10-80 keV and of about 5×

10¹² to 2×

10¹⁴ /cm², respectively.

14. The method of claim 1, wherein said third ion implantation is implanted by using n-type ions with an energy and a dosage of about 0.5-60 keV and of about 10¹⁴ to 2×

10¹⁶ /cm², respectively.

15. The method of claim 1, wherein said third ion implantation is implanted by using p-type ions with an energy and a dosage of about 0.5-60 keV and of about 10¹⁴ to 2×

10¹⁶ /cm², respectively.

16. The method of claim 1, wherein said thermal oxidation is performed at a temperature of about 700°

-1100°

C. for 0.5-120 min to form said oxide layer of about 20-100 nm and 20-100 nm in thickness on said source/drain region and on said gate structure region, respectively.