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Method to form mosfet with an inverse T-shaped air-gap gate structure

  • US 5,869,374 A
  • Filed: 04/22/1998
  • Issued: 02/09/1999
  • Est. Priority Date: 04/22/1998
  • Status: Expired due to Term
First Claim
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1. A method for fabricating a MOS transistor with an inverse T-shaped air-gap gate structure on a semiconductor substrate which has a plurality of isolation regions and a pad oxide layer on an active region of said semiconductor substrate, said method comprising the steps of:

  • forming a nitride layer on said pad oxide layer and said isolation regions;

    removing a portion of said nitride layer and said pad oxide layer, thereby leaving a remaining portion of said pad oxide layer to define a gate hollow region;

    forming a dielectric layer on said gate hollow;

    forming a first silicon layer over all areas of said semiconductor substrate;

    performing a first ion implantation into said semiconductor substrate so as to form a punchthrough stopping region in said semiconductor substrate, wherein said region is beneath said dielectric layer;

    forming an oxide layer over all surfaces of said semiconductor substrate;

    performing an anisotropic etching to etch said oxide layer to form oxide spacers on inner sidewalls of said gate hollow and leave a remaining portion of said gate hollow;

    forming a second silicon layer over all areas of said semiconductor substrate to fill said remaining portion of said gate hollow;

    removing said oxide spacers on sidewalls of said gate hollow so that a dual hollow is formed;

    etching back said second and first silicon layer until said nitride layer is exposed and a flat surface is formed;

    performing a second ion implantation so as to form LDD regions in the semiconductor substrate, wherein said regions are formed under a bottom portion of said dual hollow;

    removing said nitride layer on said pad oxide layer of said semiconductor substrate;

    removing said remaining portion of said pad oxide on said active region of said semiconductor substrate;

    performing a third ion implantation to form doped source/drain/gate regions; and

    performing a thermal oxidation so as to form an oxide layer on all exposed surfaces and to form air gap structures in sidewalls of said gate structure as well as to form an extended source/drain junction.

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