Technique for preconditioning I/Os during reconfiguration

• US 5,869,979 A
• Filed: 05/09/1996
• Issued: 02/09/1999
• Est. Priority Date: 04/05/1996
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Bocchino, Vincent T.
• Primary Examiner(s): Hudspeth, David R.
• Application Number:
  US08/647,102
• Time in Patent Office: 1,006 Days
• Field of Search: 326/38-41, 326/56, 364/490-491
• US Class Current: 326/38
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/17772 for powering on or off

Abstract

A technique for configuring programmable integrated circuits. The technique involves preconditioning or predefining the outputs and I/Os of a programmable integrated circuit before the device is programmed or reconfigured. When the device is programmed, the outputs and I/Os of the programmable integrated circuit will be driven to the preconditioned or predefined states. The technique may be implemented in conformance with the IEEE 1149.1 boundary scan architecture standard. Standard IEEE 1149.1 instructions may be used. The technique may also be used during in-system programming of programmable integrated circuits.

Claims

1. A method for reconfiguring a programmable integrated circuit comprising:

providing a user-selected input to the programmable integrated circuit;

driving a pad with the user-selected input when the programmable integrated circuit is being reconfigured, wherein the user-selected input is coupled to a first input of a multiplexer and a data path signal is coupled to a second input of the multiplexer, wherein an output of the multiplexer is coupled to the pad and a control node of the multiplexer is coupled to be controlled by a signal indicating whether the programmable integrated circuit is being reconfigured; and

reconfiguring the programmable integrated circuit.

2. The method of claim 1 wherein the user-selected input is driven through a tristate buffer.

3. The method of claim 1 wherein the programmable integrated circuit is reconfigured while on a circuit board.

4. The method of claim 1 wherein providing a user-selected input comprises storing the user-selected input into a register.

5. The method of claim 1 wherein the user-selected input is shifted serially into the programmable integrated circuit.

6. The method of claim 1 wherein the multiplexer is part of a JTAG boundary scan cell.

7. The method of claim 1 wherein driving a pad with the user-selected input comprises using an IEEE standard 1149.1 instruction.

8. A method of reconfiguring a programmable integrated circuit comprising:

transferring a first signal stored in a first register from the first register to a third register in response to an update signal;

transferring a second signal stored in a second register from the second register to a fourth register in response to the update signal;

controlling a control node of a tristate buffer with the second signal from the fourth register when the programmable integrated circuit is in a reconfigure mode; and

transferring the first signal to the tristate buffer when the programmable integrated circuit is in the reconfigure mode, wherein the first signal is driven through the tristate buffer to a pad when the second signal enables the tristate buffer, and the pad is in a high-impedance state when the second signal-disables the tristate buffer.

9. The method of claim 8 further comprising:

in response to a shift signal, linking an output of the first register to an input of the second register;

shifting the second signal through the first register into the second register; and

shifting the first signal into the first register.

10. The method of claim 8 further comprising:

initializing the first register and the second register by clearing the first register and second register.

11. The method of claim 8 wherein during controlling a control node of a tristate buffer, a multiplexer decouples a data path input from the tristate buffer and couples the first signal to the tristate buffer.

12. The method of claim 8 wherein during controlling a control node of a tristate buffer, a multiplexer decouples a tristate path input from the tristate buffer and couples the second signal to the control node of the tristate buffer.

13. The method of claim 8 further comprising:

programming the programmable integrated circuit when the programmable integrated circuit is in the reconfigure mode.

14. The method of claim 8 wherein the first register, second register, third register, and fourth register are part of a JTAG boundary scan cell.

15. The method of claim 8 wherein transferring the first signal the tristate buffer comprises using an IEEE standard 1149.1 instruction.

16. A circuit apparatus for a programmable integrated circuit comprising:

a pad;

a tristate buffer, coupled to the pad;

a first multiplexer, coupled through the tristate buffer to the pad, wherein the first multiplexer selects between a data path input and a user-selected data path input;

a second multiplexer, coupled to a control node of the tristate buffer, wherein the second multiplexer selects between a tristate path input and a user-selected tristate path input; and

a reconfiguration signal, coupled to the first multiplexer and the second multiplexer, for indicating when the programmable integrated circuit is in a reconfigure mode, wherein during the reconfigure mode, the first multiplexer couples the user-selected data path input to the tristate buffer and the second multiplexer couples the user-selected tristate path input to the control node of the tristate buffer.

17. The circuit of claim 16 further comprising:

a first register, coupled to the user-selected data path input; and

a second register, coupled to the user-selected tristate path input.

18. The circuit of claim 16 further comprising:

a third register, coupled to the first register, wherein the third register provides a clear function; and

a fourth register, coupled to the second register, wherein the fourth register provides a clear function.

19. The circuit of claim 16 wherein the data path input may be programmably coupled to the global interconnect of the programmable integrated circuit.

20. A system comprising a programmable integrated circuit as recited in claim 18.