Signal converter using multiple data streams and method therefor

• US 5,870,047 A
• Filed: 07/07/1997
• Issued: 02/09/1999
• Est. Priority Date: 07/07/1997
• Status: Expired due to Term

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: SiCOM, Inc. (Renesas Electronics Corporation)
• Inventors: Piesinger, Gregory H.
• Primary Examiner(s): Williams, Howard L.
• Assistant Examiner(s): JEAN PIERRE, PEGUY
• Application Number:
  US08/888,539
• Time in Patent Office: 582 Days
• Field of Search: 341/143, 341/144, 375/316, 375/317
• US Class Current: 341/143
• CPC Class Codes: H03M 1/662 Multiplexed conversion systems

Abstract

A signal converter (20) processes an incoming digital data stream (24) to produce an analog signal (26). A pulse shaping network (28) is configured to receive the incoming digital data stream (24) and generate a plurality of subset data streams (30). A precompensation network (32) then crosscouples the subset data streams (30) to produce crosscoupled data streams (38). Each of crosscoupled data streams (38) are then converted by respective ones of digital to analog converters (22) to produce intermediate analog signals (44). The intermediate analog signals (44) are summed by an operational amplifier (46) to produce the analog signal (26). The precompensation network (32) can be combined with the pulse shaping network (28) by using a common look-up memory element (70) to perform both functions.

Claims

1. A signal converter for processing an incoming digital data stream into an analog signal, said signal converter comprising:

means, responsive to said incoming digital data stream, for generating a plurality of subset data streams;

a precompensation network for crosscoupling said subset data streams to produce a plurality of crosscoupled data streams;

a plurality of digital to analog converters responsive to respective ones of said crosscoupled data streams; and

an analog summing circuit coupled to each of said digital to analog converters for producing said analog signal.

2. A signal converter as claimed in claim 1 wherein:

said signal converter is a modulator; and

said generating means is a pulse shaping network for converting said incoming digital data stream into a plurality of in-phase subset data streams and a plurality of quadrature-phase subset data streams.

3. A signal converter as claimed in claim 1 wherein:

said incoming digital data stream provides incoming samples; and

said generating means is configured to generate a quantity N of subset samples for each of said incoming samples where N is greater than one.

4. A signal converter as claimed in claim 3 wherein said generating means is further configured so that each of said subset data streams receives every N^th one of said subset samples.

5. A signal converter as claimed in claim 1 wherein said analog summing circuit is an operational amplifier.

6. A signal converter as claimed in claim 1 wherein:

said generating means generates a quantity N of said subset data streams; and

said precompensation network includes N differencing circuits coupled to said generating means, each of said differencing circuits being configured to process respective ones of said subset data streams.

7. A signal converter as claimed in claim 6 wherein:

said generating means generates a plurality of subset samples;

each of said subset data streams provides every N^th one of said subset samples; and

each of said differencing circuits is configured to receive a first one of said subset samples from a first one of said subset data streams and subtract a previous one of said subset samples from a another one of said subset data streams.

8. A signal converter as claimed in claim 1 wherein:

said generating means generates a quantity N of said subset data streams;

said precompensation network includes N summing circuits, wherein each of said summing circuits is configured to process a respective one of said subset data streams.

9. A signal converter as claimed in claim 8 wherein:

said generating means generates a plurality of subset samples;

each one of said subset data streams provides a first subset sample and a second subset sample;

each of said summing circuits includes a storage register configured to save said first data sample; and

each of said summing circuits is configured to add said first subset sample to said second subset sample.

10. A signal converter as claimed in claim 8 wherein said summing circuits produce respective ones of said crosscoupled data streams.

11. A signal converter as claimed in claim 1 additionally comprising a plurality of time delay components having inputs coupled to said precompensation network and having outputs coupled to respective ones of said digital to analog converters, said time delay components being configured to produce said crosscoupled data streams so that said crosscoupled data streams are temporally staggered relative to one another.

12. A signal converter as claimed in claim 11 wherein:

said incoming digital data stream exhibits a symbol period;

an output delay time is substantially equal to said symbol period divided by N;

said precompensation network produces a first one of said crosscoupled data streams and a second one of said crosscoupled data streams; and

said time delay components are configured to impart said output delay time on said second crosscoupled data stream relative to said first crosscoupled data stream.

13. A signal converter as claimed in claim 1 wherein:

said generating means produces a plurality of subset samples representative of said incoming digital data stream;

each of said digital to analog converters is configured to produce an intermediate analog signal representative of a difference between a first one of said subset samples and a second one of said subset samples; and

said analog summing circuit is configured to add said intermediate analog signal from each of said digital to analog converters to produce said analog signal.

14. A signal converter as claimed in claim 13 wherein:

said incoming digital data stream exhibits a symbol period; and

each of said digital to analog converters is configured to retain said intermediate analog signal throughout said symbol period.

15. A signal converter as claimed in claim 1 wherein:

said generating means generates subset samples having a resolution characterized by a first number of bits; and

said digital to analog converters operate at a resolution characterized by a second number of bits, said second number of bits being less than said first number of bits.

16. A signal converter as claimed in claim 1 wherein said generating means, said precompensation network, and said digital to analog converters reside on a common semiconductor substrate.

17. In a digital communication modulator, a method for providing a modulated analog signal comprising the steps of:

receiving an incoming digital data stream extending over a plurality of symbols;

producing intra-symbol samples in response to said incoming digital data stream;

converting, in a plurality of digital to analog converters, said intra-symbol samples into a corresponding plurality of intermediate analog signals; and

combining said plurality of intermediate analog signals to produce said modulated analog signal.

18. A method as claimed in claim 17 wherein:

a plurality of intra-symbol samples are configured in accordance with a sequence; and

said producing step comprises the step of configuring each of said intra-symbol samples to be responsive to a difference between one of said intra-symbol samples and a previous one of said intra-symbol samples in said sequence.

19. A method as claimed in claim 18 wherein said producing step additionally comprises the step of configuring each of said intra-symbol samples to be responsive to a difference between a first and a second one of said intra-symbol samples from a previous symbol.

20. A method as claimed in claim 19 wherein said producing step additionally comprises the step of configuring each of said intra-symbol samples to be responsive to a predetermined weighting function which defines a modulation pulse shape.

21. A method as claimed in claim 17 wherein:

said producing step produces a quantity N of intra-symbol samples during each symbol, where N is an integer number, to generate N intra-symbol data steams, wherein each of said intra-symbol data streams is generated at a symbol rate;

said quantity N of said digital to analog converters generate said quantity N of intermediate analog signals in response to said N intra-symbol data streams; and

said N digital to analog converters perform temporally staggered conversions during each symbol.

22. A method as claimed in claim 17 wherein said producing step comprises the step of performing a look-up operation in a memory element with an address input that receives said incoming digital data stream extending over said plurality of symbols.

23. A method as claimed in claim 22 wherein:

a plurality of intra-symbol samples are configured in accordance with a sequence; and

said producing step additionally comprises the step of storing, in said memory element, data configured to be responsive to a difference between each one of said intra-symbol samples and a previous one of said intra-symbol samples in said sequence, a difference between first and second ones of said intra-symbol samples from a previous symbol, and a predetermined weighting function which defines a modulation pulse shape.

24. A digital communication modulator for processing an incoming digital data stream extending over a plurality of symbols into a modulated analog signal, said modulator comprising:

a shift register responsive to said incoming digital data stream for receiving incoming samples in accordance with a sequence;

a look-up memory element configured to produce a plurality of subset data streams, each of said subset data streams being formed from an intra-symbol sample for each of said incoming samples, each of said intra-symbol samples being responsive to a difference between each one of said intra-symbol samples and a previous one of said intra-symbol samples, a difference between first and second ones of said intra-symbol samples from a previous one of said symbols, and a predetermined weighting function defining a modulation pulse shape;

a plurality of digital to analog converters responsive to respective ones of said subset data streams for producing temporally staggered intermediate analog signals; and

an operational amplifier coupled to each of said digital to analog converters and configured to combine said intermediate analog signals to produce said modulated analog signal.