LCD gate line drive circuit

• US 5,870,071 A
• Filed: 09/05/1996
• Issued: 02/09/1999
• Est. Priority Date: 09/07/1995
• Status: Expired due to Term

• Current Assignee: Eidos Advanced Display LLC
• Original Assignee: Frontech Incorporated
• Inventors: Kawahata, Ken
• Primary Examiner(s): BRIER, JEFFERY A
• Application Number:
  US08/708,588
• Time in Patent Office: 887 Days
• Field of Search: 345/98-100, 345/204-206, 345/211-213, 377/75, 377/76
• US Class Current: 345/100
• CPC Class Codes: G09G 3/3677 suitable for active matrices only

Abstract

An LCD gate line drive circuit is constituted by plural stages of TFT-LCD drive circuits which are each composed of a shift register, a set/reset flip-flop and a buffer section and which are successively driven repeatedly. A set input terminal in each stage of drive circuit is connected to an output terminal of the preceding stage of drive circuit, while a reset input terminal in each stage of drive circuit is connected to an output terminal of the succeeding stage of drive circuit, and an operating bias current in the buffer section of the stage concerned is turned ON only during the period from the start of drive in the preceding stage until the start of drive in the succeeding stage.

Claims

1. An LCD drive circuit comprising plural stages of drive circuits, said drive circuits each including:

a shift register for converting an inputted drive signal into an output signal in synchronism with an inputted synchronizing signal and outputting the output signal;

a buffer section which is driven by an operating bias current and which outputs a drive signal for driving an LCD in accordance with the output signal provided from the shift register; and

a flip-flop including a set input section for controlling said operating bias current so as to cause said buffer section to be driven by said operating bias current and a reset input section for shutting off said operating bias current for said buffer section;

wherein the set input portion of said flip-flop in each of the plural stages of drive circuits which are scanned successively with said synchronizing signal is connected to an output terminal of the preceding stage of drive circuit, said output terminal being connected to the LCD, and the reset input portion of said flip-flop in each of the plural stages of drive circuits is connected to an output terminal of the succeeding stage of drive circuit, said output terminal being connected to the LCD.

2. An LCD gate line drive circuit according to claim 1, wherein an externally generated drive signal is inputted to the set input portion of said flip-flop in the first stage of drive circuit out of the plural stages of drive circuits.

3. An LCD gate line drive circuit according to claim 1, wherein a stop signal to cut off the operating bias current in the final stage of drive circuit is inputted to the reset input portion of said flip-flop in the final stage of drive circuit.

4. An LCD gate line drive circuit according to claim 1, wherein a ratioless shift register circuit is used as said shift register.

5. An LCD gate line drive circuit according to claim 1, wherein said buffer section comprises a plurality of field effect transistor and a bootstrap circuit formed by said plural field effect transistors.