Soft switched PWM AC to DC converter with gate array logic control
First Claim
1. A soft switched PWM AC to DC converter, comprising:
- a power factor corrector converter with a boost topology that operates at a first fixed frequency;
a DC/DC converter with a forward topology that operates at a second fixed frequency;
a clock that operates at a fixed frequency that is greater than the frequency of the first fixed frequency and the second fixed frequency; and
a gate array logic IC for timing and synchronizing PWM signals for the power factor corrector converter and the DC/DC converter using the clock signal, whereby the clock signal is divided "n" times in the gate array logic IC using a synchronous divider to provide virtual monostable output signals for use in converter synchronization and gate signal timing.
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Accused Products
Abstract
A soft switched PWM AC to DC power converter for a DC power supply is disclosed. The power supply includes a power factor corrector (PFC) converter with a power boost topology, a DC/DC converter with a forward topology and a fly-back converter which serves as an auxiliary power supply for the controller components. The three converters are synchronized by a gate array logic (GAL) IC to minimize EMI noise. The GAL also conditions the PWM for the PFC and the DC/DC converter to provide very precise switching control. Synchronizing and PWM timing signals are derived by the GAL using a high-speed clock signal that is input to the GAL as a data input. The clock signal is repeatedly divided using synchronous division to yield a digital monostable timing signal that enables very precise control of converter switches.
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Citations
12 Claims
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1. A soft switched PWM AC to DC converter, comprising:
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a power factor corrector converter with a boost topology that operates at a first fixed frequency; a DC/DC converter with a forward topology that operates at a second fixed frequency; a clock that operates at a fixed frequency that is greater than the frequency of the first fixed frequency and the second fixed frequency; and a gate array logic IC for timing and synchronizing PWM signals for the power factor corrector converter and the DC/DC converter using the clock signal, whereby the clock signal is divided "n" times in the gate array logic IC using a synchronous divider to provide virtual monostable output signals for use in converter synchronization and gate signal timing. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of controlling the operation of a soft switched PWM AC to DC converter to produce a high quality DC output, comprising:
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a) operating a clock at a frequency of 2n KHz, where n is an integer greater than 2, to produce a clock signal; b) inputting the clock signal as data on an input pin of a gate array logic IC; c) repeatedly synchronously dividing the clock frequency to produce at least one digital monostable timing signal; and d) using the at least one monostable timing signal to time the PWM for the converter and to synchronize converter operations to maximize efficiency and minimize EMI noise. - View Dependent Claims (8, 9, 10, 11, 12)
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Specification
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- Resources
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Current AssigneeAstec International Limited (Emerson Electric Company)
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Original AssigneeNorthern Telecom Limited (Nortel Networks Corporation)
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InventorsCyr, Jean-Marc
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Primary Examiner(s)Hecker, Stuart N.
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Application NumberUS08/939,103Time in Patent Office501 DaysField of Search363/41, 363/65, 363/95, 323/222US Class Current363/41CPC Class CodesH02M 1/0022 the disturbance parameters ...H02M 1/44 Circuits or arrangements fo...H02M 3/33515 with digital controlH02M 3/3376 with automatic control of o...
