HDL design entry with annotated timing

• US 5,870,309 A
• Filed: 11/07/1997
• Issued: 02/09/1999
• Est. Priority Date: 09/26/1997
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Lawman, Gary R.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US08/965,846
• Time in Patent Office: 459 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/468.28, 364/578
• US Class Current: 716/102
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

The invention provides to the user a way of ascertaining the estimated delay through a circuit, by back-annotating the estimated delay through an instantiated macro into the HDL circuit description. Reported delays may include maximum delay, typical delay, and/or minimum delay on the critical path. Using well-known techniques for responding to textual keywords, a software procedure call is initiated whenever an HDL library macro instantiation is detected. The procedure looks up the associated timing data for the macro in a macro or device speeds file and back-annotates the data into the HDL circuit description, preferably as a comment directly following the macro instantiation. In another embodiment, the delay information is added when the file is saved. In yet another embodiment, the delay information is not added to the HDL file, but is written to a report file or displayed on the screen.

Claims

1. A method for annotating timing information into an HDL description, the method comprising the steps of:

a) receiving a command to instantiate a library macro, the instantiation comprising a keyword;

b) calling a timing annotation procedure in response to the keyword;

c) retrieving the macro timing information from a speeds file comprising delay information for the macro, the macro timing information comprising delays for the same path through the macro under different operating conditions; and

d) adding the timing information to the HDL description.

2. The method of claim 1, wherein the speeds file comprising delay information for the macro is a macro speeds file.

3. The method of claim 1, wherein the speeds file comprising delay information for the macro further comprises device delay data.

4. The method of claim 1, wherein in step d) when the timing information is added to the HDL description the names of the terminal nets of the critical paths are visually identified with the timing information to which they correspond.

5. The method of claim 4, wherein in step d) the names of the terminal nets of the critical path and the associated timing information are highlighted in the same color.

6. The method of claim 1, wherein the timing annotation procedure invokes synthesis of the library macro.

7. The method of claim 6, wherein the timing annotation procedure further places and routes the macro.

8. The method of claim 1, further comprising the step of:

e) adding the timing information to a log file.

9. The method of claim 1, wherein the macro timing information comprises minimum and typical delays.

10. A method for reporting macro timing information to a user editing an HDL description, the method comprising the steps of:

a) receiving a command to instantiate a library macro, the instantiation comprising a keyword;

b) calling a timing annotation procedure in response to the keyword;

c) retrieving the macro timing information from a speeds file comprising delay information for the macro, the macro timing information comprising delays for the same path through the macro under different operating conditions; and

d) displaying the timing information to the user.

11. The method of claim 10, wherein the timing annotation procedure invokes synthesis of the library macro.

12. The method of claim 11, wherein the timing annotation procedure further places and routes the macro.

13. The method of claim 10, wherein the macro timing information comprises minimum and typical delays.

14. A method for annotating timing information into an HDL description, the method comprising the steps of:

a) receiving a command to instantiate a library macro, the instantiation comprising a keyword;

b) calling a timing annotation procedure in response to the keyword;

c) retrieving the macro timing information from a speeds file comprising delay information for the macro, the macro timing information comprising delays for the macro implemented in different FPGAs; and

d) adding the timing information to the HDL description.

15. The method of claim 14, wherein the different FPGAs comprise FPGAs with different speed grades.

16. A method for reporting macro timing information to a user editing an HDL description, the method comprising the steps of:

a) receiving a command to instantiate a library macro, the instantiation comprising a keyword;

b) calling a timing annotation procedure in response to the keyword;

c) retrieving the macro timing information from a speeds file comprising delay information for the macro, the macro timing information comprising delays for the macro implemented in different FPGAS; and

d) displaying the timing information to the user.

17. The method of claim 16, wherein the different FPGAs comprise FPGAs with different speed grades.

18. A method for reporting macro delays while entering an HDL description, the method comprising the steps of:

a) specifying a delay period such that any paths having a delay within the delay period of a critical path are reported, the critical path being the slowest path through the macro;

b) receiving a command to instantiate a library macro, the instantiation comprising a keyword;

c) calling a timing annotation procedure in response to the keyword;

d) determining a critical path delay through the macro;

e) reporting the critical path delay;

f) determining one or more additional macro delays; and

g) reporting the additional delays.

19. A method for reporting macro delays while entering an HDL description, the method comprising the steps of:

a) specifying a percentage such that any paths having a delay within the specified percentage of a critical path are reported, the critical path being the slowest path through the macro;

b) receiving a command to instantiate a library macro, the instantiation comprising a keyword;

c) calling a timing annotation procedure in response to the keyword;

d) determining a critical path delay through the macro;

e) reporting the critical path delay;

f) determining one or more additional macro delays; and

g) reporting the additional delays.