High reliability logic circuit for radiation environment

• US 5,870,332 A
• Filed: 04/22/1996
• Issued: 02/09/1999
• Est. Priority Date: 04/22/1996
• Status: Expired due to Term

• Current Assignee: Aeroflex Colorado Springs Incorporated (Cobham PLC)
• Original Assignee: United Technologies Corporation (Raytheon Technologies Corporation d/b/a RTX)
• Inventors: Barry, Michael J., Gardner, Harry N., Lahey, Michael D., Harris, Debra S.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US08/635,794
• Time in Patent Office: 1,023 Days
• Field of Search: 326/11, 326/30, 365/189.05, 365/156
• US Class Current: 365/156
• CPC Class Codes: G11C 5/005 Circuit means for protection against loss of information of semiconductor storage devices
• CPC Class Codes: H03K 3/0375 provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00

Abstract

A high reliability logic circuit designed to withstand a single event upset (SEU) induced by an ion transitioning through a semiconductor structure is embodied in a memory circuit which includes a first memory cell and a second memory cell. The first and second memory cells receive a first input signal and a second input signal. The memory cells contain a logic circuit for producing a logic signal output driven by either a pullup or pulldown driver when the first and second input signals are of a desired logic state and produces a high impedance output if either input signal is not of their respective desired logic states.

The memory cells also have sufficient nodal capacitance such that the output from the first or second memory cell will not be corrupted by an SEU in the logic circuit of either the first or second memory cell.

The outputs of the first memory cell and second memory cell are further summed in analog fashion to produce a single output from the memory circuit. The summing of the output signals from the first and second memory cell prevents a single error in either memory cell from propagating to a next stage.

Claims

1. A dual memory cell having a first and second memory cell, comprising:

said first memory cell receiving a first input signal and providing a first logic signal; and

said second memory cell receiving a second input signal and providing a second logic signal, said second memory cell further receiving said first logic signal to produce a second output signal, and said first memory cell further receiving said second logic signal to produce a first output signal,

wherein said first memory cell produces said first output signal having a logic state in response to said first input signal having a first logic state and said second logic signal having an expected logic state and, said first memory cell having a high impedance at said first output signal when either said first input signal is not at said first logic state or said second logic signal is not at said expected logic state, and wherein said first memory cell has sufficient nodal capacitance to maintain said first output signal at said logic output for a time period when said high impedance is at said first output signal,

and wherein said second memory cell produces said second output signal having said logic state in response to said second input signal having said first logic state and said first logic signal having said expected logic state and, said second memory cell having said high impedance at said second output signal when either said second input signal is not at said first logic state or said first logic signal is not at said expected logic state and wherein said second memory cell has sufficient nodal capacitance to maintain said second output signal at said logic output for said time period when said high impedance is at said second output signal.

2. The dual memory cell of claim 1 wherein said first output signal of said first memory cell and said second output signal of said second memory cell are further combined in analog fashion to provide one logic state output signal.

3. The dual memory cell of claim 1 wherein said first output signal of said first memory cell and said second output of said second memory cell are provided by logic gates located in said first and second memory cells for providing said first and second output signals having outputs with active pull ups and active pull downs.

4. The dual memory cell of claim 1 wherein said first and second memory cells comprises CMOS technology.

5. The dual memory cell of claim 2 wherein said combination in analog fashion of said first output signal of said first memory cell and said second output signal of said second memory cell comprises an electrical connection having a resistance of about less than 500 ohms.

6. The dual memory cell of claim 1 wherein said first memory cell and said second memory cell comprise identical logic circuitry.

7. The dual memory cell of claim 1 wherein said first memory cell and said second memory cell are physically spaced apart to prevent an ion having an energy level of up to and including 80 MeVcm² /mg from causing SEU in both portions.

8. The dual memory cell of claim 2 wherein said combination in analog fashion of said first output signal of said first memory cell and said second output signal of said second memory cell produces said one logic state output signal having immunity to SEU at ion energy levels of up to and including 80 MeVcm² /mg.

9. The dual memory cell of claim 2 wherein said combination in analog fashion of said first output signal of said first memory cell and said second output signal of said second memory cell has a resistance of about less than 1 ohm.

10. The dual memory cell of claim 1 wherein said first and second memory cells each comprises circuits having three-state outputs wherein a first state corresponds to an output driven by V_DD, a second state corresponds to an output driven by V_SS and a third state corresponds to high resistance to both V_SS and V_DD wherein said logic state equals either said first state driven by V_DD or said second state driven by V_SS and wherein said high impedance is equal to said high resistance to both V_SS and V_DD.

11. Apparatus for performing a selected logic function on one or more logic state input signals presented thereto to provide one or more resultant logic output signals, comprising:

an input section having a signal conditioning circuit for each of the logic state input signals, for providing for each of the logic state input signals, a pair of buffered logic state signals; and

a logic section having a first and second portion, each receiving one buffered logic state signal from each of said pairs of buffered logic state signals, and each performing the selected logic function on said buffered logic state signals received thereby to each provide one or more first memory cell inputs and one or more second memory cell inputs, said first portion having a first memory cell and said second portion having a second memory cell, said first memory cell further receiving said first memory cell inputs to produce one or more first intermediate outputs, and said second memory cell further receiving said second memory cell inputs to produce said one or more second intermediate outputs, said first memory cell further receiving said second intermediate outputs to produce one or more first memory cell outputs, and said second memory cell further receiving said first intermediate signals to produce one or more second memory cell outputs,

wherein, said first memory cell outputs are a logic state output when said first memory cell inputs and said second intermediate outputs are at an expected logic state and wherein said first memory cell outputs are at a high impedance whenever said first memory cell inputs or said second intermediate outputs are not at said expected logic state and wherein said first memory cell has sufficient nodal capacitance wherein said first memory cell outputs are maintained at said logic state output for a time period when said high impedance is at said first memory cell outputs,

wherein said second memory cell outputs are said logic state output when said second memory cell inputs and said first intermediate outputs are at said expected logic state and wherein said second memory cell outputs are at said high impedance whenever said second memory cell inputs or said first intermediate outputs are not at said expected logic state, and wherein said second memory cell has sufficient nodal capacitance wherein said second memory cell outputs are maintained at said logic state output for said time period when said high impedance is at said second memory cell outputs,

and wherein each of said first memory cell outputs are combined in analog fashion with said second memory cell outputs to provide one or more logic section output signals.

12. The apparatus of claim 11 wherein said one or more first and second memory cell outputs are provided by logic gates located in said first and second memory cells for providing said one or more first and second memory cell outputs having outputs with active pull ups and active pull downs.

13. The apparatus of claim 11 wherein said first and said second portions of said logic section comprise CMOS technology.

14. The apparatus of claim 11 wherein said combination in analog fashion of said one or more first memory cell outputs and said one or more second memory cell outputs comprises an electrical connection having a resistance of about less than 500 ohms.

15. The apparatus of claim 11 wherein said first portion and said second portion of said logic section comprise identical logic circuitry.

16. The apparatus of claim 11 wherein said first portion of said logic section and said second portion of said logic section are physically spaced apart to prevent the an ion having an energy level of up to and including 80 MeVcm² /mg from causing SEU in both portions.

17. The apparatus of claim 11 wherein said output section comprises circuitry that is immune to SEU at ion energy levels of up to and including 80 MeVcm² /mg.

18. The apparatus of claim 11 wherein said one or more logic section output signals are immune to SEU at ion energy levels of up to and including 80 MeVcm² /mg.

19. The apparatus of claim 11 wherein said input section, said logic section, and said output section are on the same integrated circuit.

20. The apparatus of claim 11 wherein said input section comprises, for each of the N input signals, a pair of identical buffer stages that produce said pair of buffered signals.

21. The apparatus of claim 11 wherein for each of said pair of buffer stages, one of said pair of buffer stages is physically separated from the other of said pair of buffer stages to prevent an ion having an energy level of up to and including 80 MeVcm² /mg from causing SEU in both buffer stages.

22. The apparatus of claim 11 wherein said combination in analog fashion of said first memory cell outputs and said second memory outputs has a resistance of about less than 1 ohm.

23. The method of connecting a first memory cell having a first output and a second memory cell having a second output to provide a radiation resistant resultant output signal comprising the steps of:

presenting the first memory cell with a first input to produce a first intermediate output;

presenting the second memory cell with;

a second input to produce a second intermediate output;

presenting the first memory cell with said second intermediate output to produce said first output having a logic state when said first input and said second intermediate output are at an expected logic state and wherein said first output is at a high impedance whenever said first input or said second intermediate output are not at said expected logic state and wherein said first memory cell has sufficient nodal capacitance wherein said first output is maintained at said logic state for a time period when said first output is at said high impedance;

presenting the second memory cell with said first intermediate output to produce a second output having said logic state when said second input and said first intermediate output are at said expected logic state and wherein said second output signal is at said high impedance whenever said second input or said first intermediate output are not at said expected logic state and wherein the second memory cell has sufficient nodal capacitance wherein said second output signal is maintained at said logic output for said time period when said second output is at said high impedance; and

combining said first and second outputs in analog fashion to provide said radiation resistant resultant output signal.