Diagnostic interface system for programmable logic system development

• US 5,870,410 A
• Filed: 04/28/1997
• Issued: 02/09/1999
• Est. Priority Date: 04/29/1996
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group), Altera Corporation (Intel Corporation)
• Original Assignee: Quickturn Design Systems Incorporated (Cadence Group), Altera Corporation (Intel Corporation)
• Inventors: Patel, Rakesh H., Butts, Michael R., Sample, Stephen P., Norman, Kevin A.
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Iqbal, Nadeem
• Application Number:
  US08/840,357
• Time in Patent Office: 652 Days
• Field of Search: 371/22.2, 371/22.31, 371/22.32, 371/22.35, 371/22.5, 371/25.1, 371/27.7, 371/40.11, 371/22.1, 371/27.5, 371/27.6, 395/847, 395/182.07, 395/183.01, 395/183.06, 395/183.18, 395/183.19, 395/182.01, 364/550, 364/490, 364/580, 365/201
• US Class Current: 714/725
• CPC Class Codes: G01R 31/318516 Test of programmable logic devices [PLDs]

Abstract

An diagnostic interface system for a programmable logic system is disclosed. The diagnostic interface system provides an efficient and flexible mechanism for accessing internal nodes of programmable logic devices (PLDs) to facilitate debugging and troubleshooting of the programmable logic system. The interface system includes a diagnostic data bus connecting external I/O pins to various diagnostic data and address registers that connect to the internal circuitry of a PLD. A diagnostics controller controls the various diagnostic resources in response to user supplied control data.

Claims

1. A diagnostic interface system comprising:

a programmable logic device having programmable logic core and memory;

a diagnostic data register configured to store diagnostic data, coupled to said programmable logic core and memory, said diagnostic data register having a plurality of input/output terminals;

a diagnostic bi-directional data bus coupled to said plurality of input/output terminals;

a first plurality of external connector pins coupled to said diagnostic bi-directional data bus;

a diagnostic column address register coupled to said diagnostic bi-directional data bus and said diagnostic data register, said diagnostic column address register configured to select bits of data inside said diagnostic data register;

a diagnostic memory address register coupled to said memory and said diagnostic bi-directional data bus, said diagnostic memory address register configured to select memory cells inside memory;

a diagnostic row address register coupled to said programmable logic core and said diagnostic bi-directional data bus, said diagnostic row address register configured to select a row of configuration bits inside said programmable logic core;

a diagnostic logic address register coupled to said programmable logic core and said diagnostic bi-directional data bus, said diagnostic logic address register configured to select logic elements inside said programmable logic core; and

a diagnostic interface controller coupled to said diagnostic column address register, diagnostic memory address register, diagnostic row address register, and diagnostic logic address register via a diagnostic control bus, said diagnostic interface controller receiving external control signals from a second plurality of external connector pins.

2. The diagnostic interface system of claim 1 wherein the interface system is integrated on the same chip.

3. The diagnostic interface system of claim 2 wherein said diagnostic data register couples to said programmable logic core and memory blocks through a plurality of bi-directional data lines.

4. The diagnostic interface system of claim 2 wherein said first plurality of external connector pins are selectively usable as normal I/O pins in a non-diagnostic mode of operation of said programmable logic device.

5. A diagnostic method for a programmable logic system made up of one or more programmable logic devices, comprising the steps of:

(a) loading a diagnostic column address register with column address information for selected bits of data inside a programmable logic device;

(b) loading a diagnostic memory address register with memory address information for a selected memory cell inside the programmable logic device when memory cells are to be tested;

(c) loading a diagnostic row address register with row address information for a selected row of configuration bits inside the logic core of the programmable logic device, when said configuration bits are to be tested;

(d) loading a diagnostic logic address register with logic address information for selected logic elements inside the logic core of the programmable logic device when said logic elements are to be tested;

(e) loading diagnostic data into a diagnostic data register;

(f) coupling a selected node inside said programmable logic device to a bi-directional data line by asserting an address line in response to said column address information; and

(g) writing said diagnostic data from said diagnostic data register into said selected node via a bi-directional data line.

6. The diagnostic method of claim 5 wherein said step of writing said diagnostic data partially reconfigures said programmable logic device to test an operation of said programmable logic device.

7. The diagnostic method of claim 6 further comprising the steps of:

(h) operating the programmable logic system in a normal mode to process said diagnostic data for a predetermined period of time; and

(i) detecting a response of said programmable logic to said diagnostic data.

8. A diagnostic method for a programmable logic system made up of one or more programmable logic devices, comprising steps of:

(a) loading a diagnostic column address register with column address information for selected bits of data inside a programmable logic device;

(b) loading a diagnostic memory address register with memory address information for a selected memory cell inside a programmable logic device, when a memory cell is to be tested;

(c) loading a diagnostic row address register with row address information for a selected row of configuration bits inside the logic core of the programmable logic device, when said configuration bits are to be tested;

(d) loading a diagnostic logic address register with logic address information for selected logic elements inside a programmable logic device, when said logic elements are to be tested;

(e) coupling a selected node inside said programmable logic device to a bi-directional data line by asserting an address line in response to said column address information;

(f) loading a logic state of said selected node from said bi-directional data line into a diagnostic data register; and

(f) supplying said logic state of said selected node to external connector pins for user observation via a diagnostic bi-directional data bus.

9. The diagnostic method of claim 8 wherein said steps of loading, coupling and supplying are controlled by a diagnostic interface controller.

10. A computing system comprising:

a programmable logic device having a programmable logic core, memory, and diagnostic interface resources, said diagnostic interface resources comprising;

a diagnostic data register coupled to said programmable logic core through a plurality of bi-directional data lines;

a diagnostic bi-directional data bus coupled to said diagnostic data register and a plurality of external connector data input/output pins;

a diagnostic column address register having inputs coupled to said diagnostic bi-directional data bus, and outputs coupled to said diagnostic data register;

a diagnostic memory address register having inputs coupled to said diagnostic bi-directional data bus, and outputs coupled to memory;

a diagnostic row address register having inputs coupled to said diagnostic bi-directional data bus, and outputs coupled to said programmable logic core;

a diagnostic logic address register having inputs coupled to said diagnostic bi-directional data bus, and outputs coupled to said programmable logic core;

a diagnostic controller having a plurality of input/output terminals coupled to external connector control input/output pins; and

a diagnostic control bus coupled to said diagnostic interface controller and said address register.

11. The computing system of claim 10 wherein said programmable logic device further comprises a user memory block coupled to said plurality of bidirectional data lines.

12. The computing system of claim 11 wherein said diagnostic column address register, diagnostic memory address register, diagnostic row address register, and diagnostic logic address register are coupled to respective address decoders.

13. the computing system of claim 12 wherein said diagnostic controller is coupled to said diagnostic control bus.