ROM-based finite impulse response filter for use in mobile telephone

• US 5,870,431 A
• Filed: 06/27/1996
• Issued: 02/09/1999
• Est. Priority Date: 06/27/1996
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Black, Peter J., Easton, Kenneth D.
• Primary Examiner(s): Pham, Chi H.
• Assistant Examiner(s): Bayard, Emmanuel
• Application Number:
  US08/672,205
• Time in Patent Office: 957 Days
• Field of Search: 375/231, 375/232, 375/296, 375/350, 375/229, 364/724.19, 364/724.16, 364/724.2, 333/18, 333/28 R
• US Class Current: 375/230
• CPC Class Codes: H03H 17/0607 comprising a ROM addressed by the input data signals

Abstract

The finite impulse response (FIR) filter is implemented as a table using read-only memory (ROM). The FIR filter table stores a pre-calculated output filter value for each permissible combination of input values to be filtered. Streams of input values are successively shifted into the table and corresponding output values are successively output. In an exemplary implementation, the FIR filter is employed within a digital cellular telephone for use in smoothing a digital signal to be transmitted. The size of the required FIR filter table is minimized by exploiting constraints imposed upon the signal to be filtered and by exploiting linearity and symmetry within the filter itself. More specifically, the telephone employs a data burst randomizer to provide a data signal composed of sequences of null or 0 values and sequences of antipodal values (+1'"'"'s and -1'"'"'s). Hence, the permissible input combinations for the FIR filter include only patterns containing either all antipodal signals, all null signals, leading antipodal signals followed by trailing null signals, or leading null signals followed by trailing antipodal signals. The FIR filter look up is configured to exploit these limitations on the input streams yielding a look up table having relatively few entries. Method and apparatus implementations are disclosed.

Claims

1. A finite impulse response (FIR) filter apparatus comprising:

means for receiving an input signal stream having groups of consecutive non-null signals bracketed by groups of consecutive null signals;

means for storing FIR filter output values, wherein the means for storing stores only FIR filter output values for each of a predetermined set of unique permissible input stream patterns, with the set of permissible input stream patterns including only patterns containing either leading non-null signals followed by trailing null signals, leading null signals followed by trailing non-null signals, all non-null signals or all null signals; and

means for successively applying sequences of consecutive signals from the input signal stream to the means for storing to read out a sequence of output values corresponding to a filtered version of at least a portion of the input stream.

2. The apparatus of claim 1 wherein the non-null signals are antipodal signals.

3. The apparatus of claim 1 wherein the means for storing comprises a ROM.

4. The apparatus of claim 1 wherein the means for storing stores filter values corresponding to a symmetric FIR filter.

5. The apparatus of claim 1

wherein the permissible input stream patterns each include N signals and the groups of consecutive non-null signals each include at least N signals;

and

wherein sequences of N consecutive signals are applied to the means for storing, with N greater than 2.

6. A finite impulse response (FIR) filter apparatus for use in filtering an input signal stream, said filter apparatus comprising:

a receiver receiving an input signal stream having groups of consecutive non-null signals bracketed by groups of consecutive null signals;

a memory unit containing FIR filter output values, wherein the memory unit stores only FIR filter output values for each of a predetermined set of unique permissible input stream patterns, with the set of permissible input stream patterns including only patterns containing either leading non-null signals followed by trailing null signals, leading null signals followed by trailing non-null signals, all non-null signals or all null signals; and

an input control unit for successively applying sequences of consecutive signals from the input signal stream to memory unit to read out a sequence of output values corresponding to a filtered version of at least a portion of the input stream.

7. The apparatus of claim 6 wherein the non-null signals are antipodal signals.

8. The apparatus of claim 6 wherein the memory unit comprises a ROM.

9. The apparatus of claim 6 wherein the memory unit stores filter values corresponding to a symmetric FIR filter.

10. The apparatus of claim 6

wherein the permissible input stream patterns each include N signals and the groups of consecutive non-null signals each include at least N signals;

and

wherein sequences of N consecutive signals are applied to the memory unit, with N greater than 2.

11. A method for filtering an input signal stream, said method comprising the steps of:

receiving an input signal stream to be filtered, said input signals stream having groups of consecutive non-null signals bracketed by groups of consecutive null signals; and

successively applying sequences of consecutive signals from the input signal stream to a memory unit containing FIR filter output values to output a sequence of output values corresponding to a filtered version of at least a portion of the input stream, wherein the memory unit stores only FIR filter output values for each of a predetermined set of unique permissible input stream patterns, with the set of permissible input stream patterns including only patterns containing either leading non-null signals followed by trailing null signals, leading null signals followed by trailing non-null signals, all non-null signals or all null signals.

12. The method claim 11

wherein the permissible input stream patterns each include N signals and the groups of consecutive non-null signals each include at least N signals;

and

wherein sequences of N consecutive signals are applied to the memory unit, with N greater than 2.

13. An apparatus for converting a digital signal into an analog signal, said apparatus comprising:

means for receiving an input digital signal stream having groups of consecutive non-null signals bracketed by groups of consecutive null signals;

means for storing digital FIR filter output values, wherein the means for storing stores only FIR filter output values for each of a predetermined set of unique permissible input stream patterns, with the set of permissible input stream patterns including only patterns containing either leading non-null signals followed by trailing null signals, leading null signals followed by trailing non-null signals, all non-null signals or all null signals;

means for successively applying sequences of consecutive signals from the input digital signal stream to the means for storing to read out a sequence of digital FIR filter values corresponding to the input stream patterns; and

digital to analog conversion means for converting the sequence of digital FIR filter values into an analog signal.

14. The apparatus of claim 13 further comprising means for transmitting the analog signal.

15. The apparatus of claim 14 wherein the means for transmitting comprises a transmit unit of a cellular telephone.

16. The apparatus of claim 13 wherein the input digital signal stream is formatted in accordance with code division multiple access (CDMA) formats.

17. The apparatus of claim 13 wherein the means for storing comprises a read-only memory (ROM).

18. The apparatus of claim 14 wherein the means for transmitting comprises:

means for transmitting an in-phase analog signal; and

means for transmitting an quadrature phase analog signal.

19. The apparatus of claim 18 wherein the means for receiving the input digital signal stream comprises:

means for receiving streams corresponding to an in-phase signal; and

means for receiving streams corresponding to a quadrature phase signal.

20. The apparatus of claim 19 wherein the means for storing comprises:

an in-phase memory unit for storing sets of digital values corresponding to permissible in-phase streams; and

a quadrature phase memory unit for storing sets of digital values corresponding to permissible quadrature phase streams.

21. The apparatus of claim 13 further comprising:

means for duplicating portions of the input digital signal stream; and

means for selectively eliminating some of the duplicative portions within a predetermined time period.

22. The apparatus of claim 21 wherein each duplicative portion of the input digital signal stream comprises a power control group.

23. The apparatus of claim 21 wherein the means for selectively eliminating some of the duplicative portions of the input digital signal stream comprises a data-burst-randomizer (DBR).

24. The apparatus of claim 13 wherein the non-null signals are antipodal signals.

25. The apparatus of claim 13 wherein the digital FIR filter output values stored within the means for storing are representative of a linear, symmetric finite impulse representation of the permissible input stream patterns.

26. The apparatus of claim 13 implemented within an integrated circuit chip.

27. The apparatus of claim 13 wherein the means for storing stores separate values for four separate filter phases.

28. The apparatus of claim 27 wherein the means for storing stores partial sums representative of a 12-tap FIR filter employing forty-eight coefficients and wherein each value for each phase represents the sum of the product of six binary input values and six of the coefficients.

29. A method for converting a digital signal into an analog signal, said method comprising the steps of:

receiving an input digital signal stream having groups of consecutive non-null signals bracketed by groups of consecutive null signals;

successively applying sequences of consecutive signals from the input digital signal stream to a memory unit containing digital FIR filter output values to read out a sequence of digital FIR filter values corresponding to the input stream patterns, wherein the memory unit contains only FIR filter output values for each of a predetermined set of unique permissible input stream patterns, with the set of permissible input stream patterns including only patterns containing either leading non-null signals followed by trailing null signals, leading null signals followed by trailing non-null signals, all non-null signals or all null signals; and

converting the sequence of digital values into an analog signal.

30. The method of claim 29 further comprising the step of transmitting the analog signal.

31. The method of claim 29 wherein the received digital signals are formatted in accordance with code division multiple access (CDMA) formats.

32. The method of claim 29 further comprising the steps of:

duplicating portions of the input digital signal stream; and

selectively eliminating some of the duplicative portions within a predetermined time period before successively applying the sequences of consecutive signals to the memory unit.

33. The method of claim 32 wherein each duplicative portion of the input digital signal stream comprises a power control group.

34. The method of claim 29 wherein the non-null signals are antipodal signals.

35. An apparatus for converting a digital signal into an analog signal, said apparatus comprising:

a receiver unit connected to an input line providing an input digital signal stream having groups of consecutive non-null signals bracketed by groups of consecutive null signals;

a memory unit storing a table containing digital FIR filter output values, wherein the memory unit stores only FIR filter output values for each of a predetermined set of unique permissible input stream patterns, with the set of permissible input stream patterns including only patterns containing either leading non-null signals followed by trailing null signals, leading null signals followed by trailing non-null signals, all non-null signals or all null signals;

a shift register, connected between the receiver unit and the memory unit, said shift register successively applying sequences of consecutive signals from the input digital signal stream to the memory unit to cause the memory unit to read out a sequence of digital FIR filter values corresponding to the input stream patterns; and

a digital to analog converter connected to the memory unit, said digital to analog converter operating to convert the sequence of digital FIR filter values into an analog signal.

36. The apparatus of claim 35 wherein the non-null signals are antipodal signals.

37. The apparatus of claim 35 wherein the memory unit stores separate values for four separate filter phases.

38. The apparatus of claim 37 wherein the memory unit stores partial sums representative of a 12-tap FIR filter employing forty-eight coefficients and wherein each value for each phase represents the sum of the product of six binary input values and six of the coefficients.

39. The apparatus of claim 35

wherein the permissible input stream patterns each include N signals and the groups of consecutive non-null signals each include at least N signals;

and

wherein sequences of N consecutive signals are applied to the means for storing, with N greater than 2.