Satellite receiver tuner chip having reduced digital noise interference

• US 5,870,439 A
• Filed: 06/18/1997
• Issued: 02/09/1999
• Est. Priority Date: 06/18/1997
• Status: Expired due to Fees

• Current Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Keate, Christopher, Ben-Efraim, Nadav
• Primary Examiner(s): Chan, Jason
• Assistant Examiner(s): Corrielus, Jean B
• Application Number:
  US08/878,330
• Time in Patent Office: 601 Days
• Field of Search: 375/346, 375/316, 375/254, 375/285, 375/343, 375/348, 375/200, 375/207, 375/208, 348/725, 348/726, 348/731, 455/3.2, 455/150.1, 455/161.1, 455/161.2, 455/161.3, 370/425, 370/430
• US Class Current: 375/346
• CPC Class Codes: H04L 27/066 Carrier recovery circuits H04L27/2271 takes precedence
• CPC Class Codes: H04L 27/3863 Compensation for quadrature error in the received signal

Abstract

A DBS receiver front end which includes a tuner chip and a demodulator/decoder chip having digital interface signals. The tuner chip is configured to receive the digital signals at a reduced peak-to-peak amplitude to reduce the digital interference noise in the tuner chip. The digital signals may also have a limited slew rate to further reduce the digital interference noise. The tuner chip is configured to convert a receive signal to a baseband signal, and the demodulator/decoder chip is configured to convert the baseband signal to a decoded signal.

Claims

1. A DBS receiver front end having reduced digital noise interference which comprises:

a tuner chip coupled to receive a receive signal and configured to responsively produce a baseband signal, wherein the tuner chip is configured to receive one or more digital signals at a reduced peak-to-peak amplitude; and

a demodulator/decoder chip coupled to receive the baseband signal from the tuner and configured to convert the baseband signal to a decoded signal;

wherein said one or more digital signals includes a modulus select signal, wherein the tuner chip comprises a prescaler coupled to convert a tuning frequency signal having a tuning frequency into a reduced frequency signal having a reduced frequency by dividing tuning frequency by a first modulus when the modulus select signal is de-asserted, and wherein the prescaler divides by a second modulus when the modulus select signal is asserted.

2. The DBS receiver front end of claim 1, wherein said one or more digital signals includes a clock signal with a clock signal frequency indicative of a desired reception bandwidth, and wherein the tuner chip responsively adjusts a filter cutoff frequency to attenuate signal energy outside the desired reception bandwidth.

3. The DBS receiver front end of claim 1, wherein the reduced frequency signal is output by the tuner chip at the reduced peak-to-peak amplitude.

4. The DBS receiver front end of claim 1, wherein said one or more digital signals includes a frequency-divided signal, wherein the tuner chip comprises a phase detector coupled to receive the frequency divided signal, coupled to receive a reference frequency signal, and configured to responsively provide a phase error signal.

5. The DBS receiver front end of claim 1, wherein the baseband signal is provided to the demodulator at the reduced peak-to-peak amplitude.

6. The DBS receiver front end of claim 1, wherein the reduced peak-to-peak amplitude is less than one-tenth of a power supply voltage.

7. The DBS receiver front end of claim 1, wherein the reduced peak-to-peak amplitude is between 50 mV and 120 mV.

8. A DBS receiver front end having reduced digital noise interference which comprises:

a tuner chip coupled to receive a receive signal and configured to responsively produce a baseband signal, wherein the tuner chip is configured to receive one or more digital signals having a reduced slew rate; and

a demodulator/decoder chip coupled to receive the baseband signal from the tuner and configured to convert the baseband signal to a decoded signal;

wherein the reduced slew rate is a ratio of a peak-to-peak voltage over a transition time, and wherein the transition time is greater than one-tenth of a minimum cycle time of said one or more digital signals.

9. The DBS receiver front end of claim 8, wherein said one or more digital signals includes a clock signal with a clock signal frequency indicative of a desired reception bandwidth, and wherein the tuner chip responsively adjusts a filter cutoff frequency to attenuate signal energy outside the desired reception bandwidth.

10. The DBS receiver front end of claim 8, wherein said one or more digital signals includes a modulus select signal, wherein the tuner chip comprises a prescaler coupled to convert a tuning frequency signal having a tuning frequency into a reduced frequency signal having a reduced frequency by dividing tuning frequency by a first modulus when the modulus select signal is de-asserted, and wherein the prescaler divides by a second modulus when the modulus select signal is asserted.

11. The DBS receiver front end of claim 10, wherein the reduced frequency signal is output by the tuner chip with the reduced slew rate.

12. The DBS receiver front end of claim 8, wherein said one or more digital signals includes a frequency-divided signal, wherein the tuner chip comprises a phase detector coupled to receive the frequency divided signal, coupled to receive a reference frequency signal, and configured to responsively provide a phase error signal.

13. A method for reducing digital noise interference induced by high frequency digital signals, wherein the method comprises:

receiving one or more high frequency digital signals having a peak-to-peak voltage amplitude; and

limiting the peak-to-peak voltage amplitude of said one or more high frequency digital signals to less than one-tenth of a power supply voltage;

wherein the method further comprises providing said one or more high frequency digital signals at a reduced slew rate, wherein the reduced slew rate is a ratio of the peak-to-peak voltage over a transition time, and wherein the transition time is greater than one-tenth of a minimum cycle time of said one or more digital signals.

14. A DBS receiver front end having reduced digital noise interference which comprises:

a tuner chip coupled to receive a receive signal and configured to responsively produce a baseband signal, wherein the tuner chip is configured to receive one or more digital signals having a reduced slew rate; and

a demodulator/decoder chip coupled to receive the baseband signal from the tuner and configured to convert the baseband signal to a decoded signal;

wherein said one or more digital signals includes a modulus select signal, and wherein the tuner chip comprises a prescaler coupled to convert a tuning frequency signal having a tuning frequency into a reduced frequency signal having a reduced frequency by dividing tuning frequency by a first modulus when the modulus select signal is de-asserted, and wherein the prescaler divides by a second modulus when the modulus select signal is asserted.

15. The DBS receiver front end of claim 14, wherein said one or more digital signals includes a clock signal with a clock signal frequency indicative of a desired reception bandwidth, and wherein the tuner chip responsively adjusts a filter cutoff frequency to attenuate signal energy outside the desired reception bandwidth.

16. The DBS receiver front end of claim 14, wherein the reduced frequency signal is output by the tuner chip with the reduced slew rate.

17. The DBS receiver front end of claim 14, wherein said one or more digital signals includes a frequency-divided signal, wherein the tuner chip comprises a phase detector coupled to receive the frequency divided signal, coupled to receive a reference frequency signal, and configured to responsively provide a phase error signal.