Computer system capable of outputting status data without interrupting execution of program

• US 5,870,541 A
• Filed: 02/07/1996
• Issued: 02/09/1999
• Est. Priority Date: 02/07/1995
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Tamura, Toshinori
• Primary Examiner(s): PALYS, JOSEPH E
• Application Number:
  US08/597,801
• Time in Patent Office: 1,098 Days
• Field of Search: 395/184.01, 395/182.09, 395/183.01, 395/183.13, 395/183.2, 395/185.01, 395/183.04, 395/183.16, 395/183.05, 395/183.06, 395/183.07, 364/266, 364/264.6, 364/963.9, 364/232.3
• US Class Current: 714/47.1
• CPC Class Codes: G06F 11/2736 using a dedicated service processor for test
• CPC Class Codes: G06F 11/3636 by tracing the execution of the program
• CPC Class Codes: G06F 11/3652 in-circuit-emulation [ICE] arrangements

Abstract

A computer system such as a debugging system for a microcomputer system includes a display unit and a supervisor for receiving at least one of the plurality of status data from the microcomputer system independently from the execution of a program in the microcomputer system and displaying the read status data on the display unit. The microcomputer system includes the plurality of peripheral circuits respectively having status flags, each of which stores the status data of the corresponding peripheral circuit, and a CPU executing the program. The status data are updated as the execution of the program and the CPU can read the status data of each of the status flags. An emulation control circuit generates a status clock signal independently from the execution of the program by the CPU and a selector sequentially and repeatedly selects one of the plurality of status data in response to the status clock signal to output the selected status data to the supervisor.

Claims

1. A computer system comprising:

a bus;

a central processing unit (CPU) connected to the bus, for executing a program;

a plurality of peripheral circuits connected to the bus and respectively having status flags, each of which stores status data of a corresponding peripheral circuit, wherein each status data is capable of being changed during the execution of the program by said CPU, and wherein said CPU can read said each status data;

control signal generating means for continuously generating a control signal independently from the execution of the program by said CPU, such that said status data are sequentially and repeatedly outputted,

selecting means connected to said status flags, for selecting one of said status data in response to said control signal to output the selected status data to an external circuit other than said CPU, and

wherein said selecting means comprises;

a counter for counting said control signal; and

a selector for selectively outputting said plurality of status data in response to the count of said counter.

2. A computer system according to claim 1, wherein said control signal generating means outputs said control signal to said external circuit to indicate one of the plurality of peripheral circuits corresponding to the selected status data.

3. A computer system according to claim 1, wherein said control signal generating means generates said control signal in response to a clock signal from said external circuit.

4. A method of acquiring a plurality of status data indicative of statuses of a plurality of peripheral circuits without interrupting the execution of a program by a CPU, comprising the steps of:

changing said plurality of status data of said plurality of peripheral circuits during the execution of the program by the CPU without direct relation to the execution of the program by the CPU, wherein the CPU can read said plurality of status data;

continuously generating a control signal independently from the execution of the program by said CPU, such that said plurality of status data are sequentially and repeatedly outputted;

counting said control signal; and

selectively outputting said plurality of status data in response to the count.

5. A method according to claim 4, wherein said generating step includes continuously generating said control signal such that said plurality of status data are time-divisionally outputted.

6. A method according to claim 5, wherein said selectively outputting step includes:

decoding said count to provide a decoded result; and

specifying one of said plurality of status data in accordance with the decoded result.

7. A method according to claim 5, further comprising the step of interrupting the execution of the program in response to said outputted status data.

8. A method according to claim 6, wherein said outputting step includes:

sequentially selecting one of said plurality of status data of said peripheral circuits based on the count; and

outputting the selected status data to an external circuit and said generating step further includes outputting said control signal to said external circuit to indicate one of the plurality of peripheral circuits corresponding to the selectively outputted status data.

9. A method according to claim 4, wherein said generating step includes generating said control signal in response to a clock signal from said external circuit.

10. A method according to claim 4, further comprising the step of displaying said selectively outputted status data by said external circuit.

11. A computer system for a microcomputer system comprising:

a display unit;

a microcomputer system for executing a program, wherein said microcomputer system includes a central processing unit (CPU), a plurality of peripheral circuits, and a plurality of status data indicative of whether a state of each of said plurality of peripheral circuits has changed during the execution of the program, and said CPU is configured to read said plurality of status data;

a supervisor for receiving at least one of said plurality of status data from said microcomputer system independently from the execution of the program in said microcomputer and displaying the received status data on said display unit;

wherein said CPU executes the program;

said plurality of peripheral circuits respectively having status flags, each of which stores said status data of said corresponding peripheral circuit;

said microcomputer system further comprising;

control signal generating means for continuously generating a control signal independently from the execution of the program by said CPU, such that said plurality of status data are sequentially and repeatedly outputted;

selecting means connected to said status flags, for selectively outputting said plurality of status data to said supervisor in response to said control signal, and

wherein said selecting means comprises;

a counter for counting said control signal; and

a selector for selectively outputting said plurality of status data in response to the count of said counter.

12. A computer system according to claim 11, wherein said control signal generating means outputs said control signal to said supervisor to indicate one of the plurality of peripheral circuits corresponding to the selected status data, and said supervisor identifies the received status data based on said control signal.

13. A computer system according to claim 11, wherein said supervisor interrupts the execution of the program in said CPU when said supervisor detects from said selected status data that the state of one of said plurality of peripheral circuits corresponding to said selected status data is changed.

14. A computer system according to claim 11, wherein said supervisor issues a clock signal to said control signal generating means.

15. A computer system comprising:

a bus;

a central processing unit (CPU) for executing a program, said CPU being connected to the bus;

a plurality of peripheral circuits connected to the bus and respectively having status flags, each of which stores status data of a corresponding peripheral circuit, each status data being capable of being changed during the execution of the program by said CPU;

control signal generating means for continuously generating a control signal independently from the execution of the program by said CPU such that said plurality of status data are sequentially and repeatedly outputted; and

selecting means connected to said status flags, for selecting one of said plurality of status data in response to said control signal to output the selected status data to an external circuit other than said CPU,

wherein said selecting means comprises;

a counter for counting said control signal; and

a selector for selectively outputting said plurality of status data in response to the count of said counter.

16. A computer system according to claim 15, wherein said control signal generating means outputs said control signal to said external circuit.

17. A computer system according to claim 15, wherein said control signal generating means generates said control signal in response to a selection control signal from said external circuit.

18. A method of acquiring a plurality of status data indicative of statuses of a plurality of peripheral circuits without interrupting the execution of a program by a CPU, comprising the steps of:

setting said plurality of status data in said plurality of peripheral circuits during the execution of the program by the CPU;

generating a control signal independently from the execution of the program by said CPU; and

selecting and outputting one of said plurality of status data in response to said control signal, and

wherein said generating step includes continuously generating said control signal such that said plurality of status data are sequentially and repeatedly outputted, and

wherein said selecting step includes;

counting said control signal;

decoding said count; and

specifying one of said plurality of status data in accordance with a result of the decoding step.

19. A method according to claim 18, wherein said outputting step includes outputting the selected status data to an external circuit and said generating step further includes outputting said control signal to said external circuit.

20. A method according to claim 18, wherein said generating step includes generating said control signal in response to a clock signal from said external circuit.

21. A method according to claim 18, further comprising the step of displaying said selected status data by said external circuit.

22. A method according to claim 18, further comprising the step of interrupting the execution of the program in accordance with said outputted status data.