Transistor switch used to isolate bus devices and/or translate bus voltage levels

• US 5,870,573 A
• Filed: 10/18/1996
• Issued: 02/09/1999
• Est. Priority Date: 10/18/1996
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Johnson, Leith L.
• Primary Examiner(s): An, Meng-Ai T.
• Assistant Examiner(s): Thlang, Eric S.
• Application Number:
  US08/733,483
• Time in Patent Office: 844 Days
• Field of Search: 395/309, 395/449, 395/496, 395/427, 395/287, 395/444, 395/474-478, 395/494, 395/428, 395/311, 364/200, 365/145
• US Class Current: 710/316
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence

Abstract

A plurality of MOSFET switches, one per bus line, are used to solve the problem of interfacing between two incompatible devices via a single shared bus. The MOSFET switches used are simple, inexpensive, and very fast. The switches perform two primary functions: 1) isolation of two bus sections (possibly for loading reasons); and 2) translation of incompatible voltages transmitted over the bus.

Claims

1. Simplified apparatus for transmitting data to and from a plurality of incompatible devices via a common bus, and for allowing each of the plurality of incompatible devices to receive data transmitted to or from another of the plurality of incompatible devices, the apparatus comprising:

a) a shared data bus;

b) a plurality of devices connected to the shared data bus, the plurality of devices comprising at least first and second devices;

c) a number of field effect transistors having source and drain terminals, wherein each of the number of field effect transistors bridges a single line of the shared data bus view said source and drain terminals, at a point in between points where the first and second devices connect to the shared data bus; and

d) at least one voltage regulator, each of the at least one voltage regulators being connected to one or more gate terminals of the number of field effect transistors.

2. Apparatus as in claim 1, further comprising a controller, wherein the controller is connected to:

a) the shared data bus;

b) each of the at least one voltage regulators; and

c) each of the plurality of devices connected to the shared data bus;

wherein the controller may regulate the configuration of, and flow of data over, the shared data bus.

3. Apparatus as in claim 2, wherein:

a) the first device is a cache memory;

b) the second device is a main memory; and

c) the controller is a memory controller.

4. Apparatus as in claim 3, wherein:

a) the first device places a heavy load on the shared data bus; and

b) the second device places a light load on the shared data bus.

5. Apparatus as in claim 3, wherein:

a) the memory controller and cache memory are 3.3 V components; and

b) the main memory is a 5 V component.

6. Apparatus as in claim 3 wherein each of the number of field effect transistors is a metal-oxide semiconductor field effect transistor.

7. Apparatus as in claim 1, wherein each of the number of field effect transistors is a metal-oxide semiconductor field effect transistor (MOSFET).

8. Apparatus as in claim 7, wherein each of the MOSFETs is an n-channel MOSFET.

9. Apparatus as in claim 1, further comprising:

additional field effect transistors having source and drain terminals, wherein;

i) each of the additional field effect transistors bridges a single line of the shared data bus via said source and drain

terminals, at a point in between points where various of the plurality of integrated circuit devices connect to the bus, but not in between points where the first and second devices connect to the bus; and

ii) wherein a gate terminal of each additional field effect transistor is connected to one of at least one additional voltage regulators.

10. Apparatus as in claim 1, wherein each of the at least one voltage regulators:

connects to a plurality of gate terminals of the number of field effect transistors, and synchronously regulates a voltage applied to each of the plurality of gate terminals.

11. Apparatus as in claim 1, wherein:

a) the first device places a light load on the shared data bus; and

b) the second device places a heavy load on the shared data bus.

12. Apparatus as in claim 1, wherein each of the at least one voltage regulators comprises:

a) a buffer, the buffer comprising a data input, a data output, and a supply voltage input; and

b) a diode connected between the supply voltage input and a voltage source;

wherein;

c) the data output is connected to one or more gate terminals of the number of field effect transistors; and

d) the data input receives an enable signal.

13. A method of selectively isolating a high speed access memory from a heavily loaded memory, the method comprising the steps of:

a) connecting the high speed access and heavily loaded memories to a common bus;

b) bridging each line of the common bus with a field effect transistor switch, at a point in between points where the high speed access memory and heavily loaded memory are connected to the common bus, each bridge being formed via connections to the source and drain terminals of a field effect transistor; and

c) when desiring to isolate the high speed access memory from the heavily loaded memory, opening each field effect transistor switch by applying an appropriate voltage to the gate terminal.

14. A method of updating a cache memory while reading a main memory, the method comprising the steps of:

a) connecting the cache memory and main memory to a common bus;

b) bridging each line of the common bus with a field effect transistor switch, at a point in between points where the cache memory and main memory are connected to the common bus, each bridge being formed via connections to the source and drain terminals of a field effect transistor;

c) when desiring to update the cache memory while reading the main memory;

i) closing each field effect transistor switch by applying an appropriate voltage to the gate terminal; and

ii) substantially simultaneously;

A) disabling output buffers of the cache memory;

B) enabling input buffers of the cache memory; and

C) driving lines of the common bus with data stored in main memory.

15. A method as in claim 14, wherein the step of applying an appropriate voltage to the gate terminal of a field effect transistor switch comprises:

regulating the applied voltage so as to attenuate signals passing through the field effect transistor switch, said attenuation being to a voltage level tolerated by the cache memory.

16. A method of transmitting data across a common bus connected to a plurality of devices, the method comprising the steps of:

a) bridging each line of the common bus with a field effect transistor switch, at a point in between points where first and second devices are connected to the common bus, each bridge being formed via connections to the source and drain terminals of a field effect transistor;

b) before the first device transmits data across the common bus, opening each field effect transistor switch by applying a first voltage to the gate terminal; and

c) before the second device transmits data across the common bus, closing each field effect transistor switch by applying a second voltage to said gate terminal.

17. A method as in claim 16, wherein the step of applying a second voltage to the gate terminal of a field effect transistor switch comprises:

regulating the second voltage so as to attenuate signals passing through the field effect transistor switch, said attenuation being to a voltage level tolerated by both the first and second devices.