Computer system employing streaming buffer for instruction preetching

• US 5,870,599 A
• Filed: 10/17/1997
• Issued: 02/09/1999
• Est. Priority Date: 03/01/1994
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Gupta, Ashwani K., Shenoy, Sunil R., Hinton, Glenn J.
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): Coulter, Kenneth R.
• Application Number:
  US08/953,226
• Time in Patent Office: 480 Days
• Field of Search: 395/586, 395/585, 711/207
• US Class Current: 712/239
• CPC Class Codes: G06F 12/0859 with reload from main memory
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 2212/6022 Using a prefetch buffer or dedicated prefetch cache
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3814 Implementation provisions of instruction buffers, e.g. prefetch buffer; banks

Abstract

Streaming buffer renaming for memory accesses issued by a microprocessor to an external memory via a system bus allows up to N fetch accesses at any one time for M physical streaming buffer locations, where N is greater than M. When a fetch within the processor misses the instruction cache, the fetch address is placed in the streaming buffer. When the data has been fetched from the external memory, it is returned to the streaming buffer and placed into one of the M physical buffer locations. The data within the streaming buffer is returned to the instruction cache of the processor only if it is to be used in accordance with the computer program being executed.

Claims

1. A computer system for executing a computer program comprising:

a system bus;

a memory coupled to said system bus;

an instruction cache storing frequently referenced instructions to be executed in said computer program;

a logic unit managing transfer to/from said memory via said system bus;

an instruction streaming buffer (ISB) coupled to said instruction cache and said logic unit, said ISB having M physical buffers associated with N virtual identifiers, where M and N are integers and M is less than N;

said ISB sending external fetch requests to said logic unit to fetch instructions from said memory, each external fetch request being assigned a virtual identifier corresponding to a physical buffer, said physical buffer being renamed with a different virtual identifier for a new external fetch request in the event of a branch misprediction; and

wherein said ISB forwards data returned by each said fetch request to said instruction cache only if said data is to be used by said computer program.

2. The computer system of claim 1 further comprising an instruction fetch unit (IFU) coupled to said instruction cache, logic unit and ISB for fetching instructions to be executed in accordance with said computer program.

3. The computer system of claim 2 further comprising a translation buffer containing the virtual-to-physical translations of said ISB.

4. The computer system of claim 2 wherein said instruction cache, ISB and IFU are contained on a single integrated circuit comprising a processor.

5. The computer system of claim 4 further comprising a secondary cache memory coupled to said processor, said secondary cache memory being coupled to said logic unit.

6. The computer system of claim 5 further comprising a translation buffer containing the virtual-to-physical translations of said ISB.

7. The computer system of claims 1, 2, 3, 4, 5 or 6 wherein said translation buffer comprises M entries with each entry containing a first bit indicating a valid virtual-to-physical translation.

8. The computer system of claim 7 wherein said translation buffer further comprises a second bit indicating that a fetch for a particular entry has been issued to said logic unit against the virtual identifier corresponding to said particular entry.

9. The computer system of claim 8 wherein M is equal to 2 and N is equal to 4.

10. A computer system comprising:

a microprocessor having a pipeline for speculatively executing a program;

a memory;

an external bus coupling said memory to said microprocessor;

said microprocessor including an instruction fetch unit (IFU) for fetching instructions to be executed for said program, and a bus logic unit communicating with said IFU and said external bus;

said IFU sending an external fetch request to said bus logic unit to fetch an instruction from said memory via said external bus, said IFU further comprising an instruction streaming buffer (ISB) including M physical buffers having N virtual identifiers, where M and N are integers and M is less than N, said ISB tracking up to N outstanding fetch requests of said IFU by allocating a virtual identifier to a physical buffer for each said outstanding fetch request, said physical buffer being renamed with a different virtual identifier in the event of a mispredicted branch; and

wherein data returned to said ISB for each said fetch request is forwarded to said IFU only if it is to be used by said program.

11. The computer system of claim 10 wherein said IFU comprises an instruction cache coupled to said ISB for receiving data forwarded by said ISB.

12. The computer system of claim 11 wherein said IFU further comprises a victim cache coupled to said instruction cache, said victim cache saving data expelled from said instruction cache.

13. The computer system of claim 10 wherein said ISB further comprises a translation buffer containing the virtual-to-physical translations of said ISB.

14. The computer system of claim 10 wherein said instruction cache, ISB and IFU are integrated on the same silicon substrate as said microprocessor.

15. The computer system of claim 14 further comprising a secondary cache memory coupled to said microprocessor, said secondary cache memory being fabricated on a separate integrated circuit.

16. The computer system of claim 15 further comprising a translation buffer containing the virtual-to-physical translations of said ISB.

17. The computer system of claim 12 wherein IFU selects a fetch address of a next cache access in a first pipestage of said pipeline.

18. The computer system of claim 17 wherein said IFU accesses said ISB, instruction cache, and victim cache in parallel in a second pipestage of said pipeline using said fetch address.

19. The computer system of claim 18 wherein said fetch address is a linear address.

20. The computer system of claim 18 wherein during said second pipestage of said pipeline, in the event that said fetch address misses said ISB, instruction cache, or victim cache, said IFU sends said external fetch request to said bus logic unit.

21. The computer system of claims 10, 11, 12, 13, 14, 15, 16, 17, 18, 19 or 20 wherein said translation buffer comprises M entries with each entry containing a first bit indicating a valid virtual-to-physical translation.

22. The computer system of claim 21 wherein said translation buffer further comprises a second bit indicating that a fetch for a particular entry has been issued to said logic unit against the virtual identifier corresponding to said particular entry.

23. The computer system of claim 22 wherein M is equal to 2 and N is equal 4.

24. A computer system comprising:

a microprocessor having a pipeline for speculatively executing a program;

a memory;

a bus coupling said memory to said microprocessor;

said microprocessor including an instruction fetch unit (IFU) for fetching instructions to be executed for said program, a mechanism coupled to said IFU providing branch prediction information, and a bus logic unit communicating with said IFU and said bus;

said IFU sending a fetch request to said bus logic unit to fetch an instruction from said memory via said bus, said IFU further comprising an instruction streaming buffer (ISB) including M physical buffers having N virtual identifiers, where M and N are integers and M is less than N, said ISB tracking up to N outstanding fetch requests of said IFU by allocating a virtual identifier to a physical buffer for each said outstanding fetch request, said IFU assigning a new virtual identifier to said physical buffer in the event of a mispredicted branch; and

wherein data returned to said ISB for each said fetch request is forwarded to said IFU only if it is to be used by said program.

25. The computer system of claim 24 wherein said IFU comprises an instruction cache coupled to said ISB for receiving data forwarded by said ISB.

26. The computer system of claim 25 wherein said ISB further comprises a translation buffer that translates said N virtual identifiers into said M physical buffers, said translation buffer having M entries with each entry containing a first bit indicating a valid virtual-to-physical translation.

27. The computer system of claim 26 wherein an entry of said translation buffer further includes a second bit indicating that a pending fetch request has been issued to said bus logic unit against a virtual identifier corresponding to said entry.

28. The computer system of claim 24 wherein said memory comprises a secondary cache memory.

29. The computer system of claim 24 wherein M is equal to 2 and N is equal 4.

30. A computer system comprising:

an out-of-order computing machine that executes instructions of a program based on data dependencies and execution resource availability;

a main memory;

a first bus coupling said main memory to said out-of-order computing machine;

said out-of-order computing machine including an instruction fetch unit (IFU) for fetching instructions to be executed in said program, and a bus logic unit communicating with said IFU and said first bus;

said IFU sending a fetch request to said bus logic unit to fetch an instruction from said main memory via said first bus, said IFU further comprising an instruction streaming buffer (ISB) including M physical buffers having N virtual identifiers, where M and N are integers and M is less than N, said ISB tracking up to N outstanding fetch requests of said IFU by allocating a virtual identifier to a physical buffer for each said outstanding fetch request, said outstanding fetch requests being returned to said ISB in an arbitrary order.

31. The computer system of claim 30 further comprising circuitry coupled to said IFU providing branch prediction information, wherein said IFU assigns a new virtual identifier to said physical buffer in the event of a mispredicted branch.

32. The computer system of claim 31 wherein said IFU further comprises an instruction cache coupled to said ISB for receiving data forwarded by said ISB.

33. The computer system of claim 32 wherein said ISB further comprises a translation buffer that translates said N virtual identifiers into said M physical buffers, said translation buffer having M entries with each entry containing a first bit indicating a valid virtual-to-physical translation.

34. The computer system of claim 33 wherein an entry of said translation buffer further includes a second bit indicating that a pending fetch request has been issued to said bus logic unit against a virtual identifier corresponding to said entry.

35. The computer system of claim 30 further comprising:

a secondary cache memory;

a second bus coupling said secondary cache memory to said out-of-order computing machine; and

wherein said out-of-order computing machine further includes a local instruction cache, said IFU sending said fetch request to said bus logic unit to fetch said instruction in response to a miss to said local instruction cache.

36. The computer system of claims 30, 31, 32, 33, 34, or 35 wherein M is equal to 2 and N is equal 4.