Device for the computer linking of apparatuses with heterogeneous communication systems, and key pertaining to such a device

• US 5,870,626 A
• Filed: 09/17/1996
• Issued: 02/09/1999
• Est. Priority Date: 04/08/1994
• Status: Expired due to Fees

• Current Assignee: Ishikawa Seisakusho, Tadaoki Mitani
• Original Assignee: Ishikawa Seisakusho, Tadaoki Mitani
• Inventors: Lebeau, Luc
• Primary Examiner(s): Kriess, Kevin A.
• Application Number:
  US08/714,094
• Time in Patent Office: 875 Days
• Field of Search: 395/651, 395/652, 395/653, 395/712, 395/828, 395/830, 395/831, 395/834
• US Class Current: 710/11
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: H01R 13/64 Means for preventing incorrect coupling
• CPC Class Codes: H01R 13/665 with built-in electronic circuit H01R13/70, H01R13/719 take precedence
• CPC Class Codes: H04L 69/18 Multiprotocol handlers, e.g. single devices capable of handling multiple protocols

Abstract

A device (L) for transferring data between heterogeneous apparatuses (1, 2, 3 and 4) and one or more computers (18 and 19). An interface (20) is automatically configured by loading and executing specific protocol conversion programs and adapting the physical link on the basis of recognition of the connecting cable (5, 6, 7, 8, 16 or 17) between the interface and the computer(s) and apparatus(es) to be connected. The connecting cable is recognized by entering a key (k5, k6, k7, k8, k16 or k17) in the cable in the form of one or more electrical or electronic components providing nonambiguous identification of the cable.

Claims

1. A computer-peripheral interfacing system accommodating heterogeneous protocol requirements to flexibly link computers and peripheral apparatuses to one another, the system comprising:

a peripheral apparatus link cable designed for connecting to a first peripheral apparatus, said peripheral apparatus link cable comprising a peripheral identification key for identifying the first peripheral apparatus and an end terminated with a standard peripheral connector;

a computer link cable designed for connecting to a first computer, said computer link cable comprising a computer identification key for identifying the first computer and an end terminated with a standard computer connector; and

a connecting interface unit for linking the first peripheral apparatus to the first computer, said connecting interface unit comprising;

a peripheral cable plug designed to accept said standard peripheral connector of said peripheral apparatus link cable,

a computer cable plug designed to accept said standard computer connector of said computer link cable,

a first channel processor operatively connected with said peripheral cable plug, and designed to communicate with said peripheral apparatus link cable via said peripheral cable plug to ascertain said peripheral identification key for identifying the first peripheral apparatus,

a second channel processor operatively connected with said computer cable plug, and designed to communicate with said computer link cable via said computer cable plug to ascertain said computer identification key for identifying the first computer, and

a central processor operatively connected to said first and second channel processors and to a library of protocol conversion programs, and designed to configure said first channel processor based on a first protocol conversion program associated with said peripheral identification key and to configure said second channel processor based on a second protocol conversion program associated with said computer identification key,

wherein said first and second channel processors are designed to be configured, on a software level, by said first and second conversions programs respectively so that said first and second channel processors communicate, via said peripheral apparatus link cable and said computer link cable respectively, with the first peripheral apparatus and the first computer respectively, and bidirectionally transfer information between the first peripheral apparatus and the first computer.

2. The system of claim 1, wherein said first and second conversion programs further comprise hardware-level protocol data relating to the first peripheral apparatus and the first computer respectively, and

said first and second channel processors further comprise circuitry designed to be configured, on at least one of said software level and said hardware level, by said first and second conversion programs.

3. The system of claim 2, further comprising:

a plurality of said peripheral apparatus link cable, each of said plural peripheral apparatus link cables adapted for connecting one of plural peripheral apparatuses having heterogeneous peripheral protocol requirements; and

a plurality of said computer link cable, each of said plural computer link cables adapted for connecting one of plural computers having heterogeneous computer protocol requirements,

wherein said peripheral identification key associated with each of said plural peripheral apparatus link cables identifies the one of the plural peripheral apparatuses associated therewith, and said computer identification key associated with each of said plural computer link cables identifies the one of the plural computers associated therewith, so that upon any of the plural peripheral apparatuses and any of the plural computers being connected to said connecting interface unit with associated peripheral apparatus link and computer link cables, said central processor can configure said first and second channels to enable bilateral communications therebetween after ascertaining said associated peripheral and computer identification keys.

4. The system of claim 3, wherein said first and second channel processors further comprise circuitry designed to be configured, on both of said software level and said hardware level.

5. The system of claim 3, further comprising:

plural peripheral channels, each of said plural peripheral channels comprising one of said peripheral cable plug operatively connected to one of said first channel processor, each said first channel processor further comprising a first microprocessor and first and second communication lines; and

plural computer channels, each of said plural computer channels comprising one of said computer cable plug and said second channel processor, each said second channel processor further comprising a second microprocessor and third and forth communication lines,

wherein each of said plural peripheral channels and said plural computer channels are designed and adapted to communicate both with said central processor and another of said plural peripheral channels and said plural computer channels.

6. The system of claim 1, wherein said peripheral identification key and said computer identification key further comprise a read only memory storing data identifying the first peripheral apparatus and the first computer respectively.

7. The system of claim 1, wherein each of said peripheral identification key and said computer identification key further comprise one of a ROM, an EEPROM, an EPROM, a flash memory, and a random access memory backed up by battery, storing data identifying the first peripheral apparatus and the first computer respectively.

8. The system of claim 1, wherein said peripheral identification key is located adjacent said standard peripheral connector.

9. The system of claim 1, wherein said peripheral identification key is integral to said standard peripheral connector.

10. The system of claim 1, wherein said peripheral identification key is designed and adapted to be removable from said peripheral apparatus cable.

11. A computer link device for linking one or more apparatuses with heterogeneous communication protocols and one or more computers with heterogeneous communication protocols, comprising an interface, link cables, and identification keys associated with said link cables,

said link cables designed and adapted for connection between said interface and the apparatuses and the computers that are to be linked,

said interface comprising plural plugs for connection to said link cables, plural channel processors capable of being configured at the software level following the reading of said identification keys associated with said link cables, a library of protocol conversions programs, and a central processor operatively connected to said plural channel processors and to said library,

wherein said central processor is designed and adapted to select from said library, based on said identification keys, software protocol information to configure said plural channel processors to enable bidirectional transfer of information between the apparatuses and the computers connected to said interface.

12. The device of claim 11, wherein each of said plural channel processors further comprise plural switchable circuits, each of said circuits adapted to a particular hardware-level protocol so that said plural channel processors are hardware-level protocol configurable,

wherein said interface is designed and adapted to determine hardware-level protocol configuration requirements of the apparatuses and computers that are to be linked, and to configure said plural channel processors accordingly, based on said identification key associated with said link cable connected to said each of said plural channels.

13. The device of claim 12, wherein each of said link cables further comprise one of said identification keys.

14. The device of claim 11, wherein each of said channel processors comprise a microprocessor and two communications lines adapted to, respectively:

1) communicate with the apparatuses or computers linked to said interface via said link cables so that the apparatuses and computers bidirectionally transfer information therebetween, and

     2) to read said identification keys.

15. The device of claim 13, wherein each of said identification keys comprise an electrical or electronic component.

16. The device of claim 15, wherein said electrical or electronic component further comprises at least one of a ROM, an EEPROM, an EPROM, a flash memory, and a random access memory backed up by a battery.

17. The device of claim 16, wherein said identification keys are connected to said link cables along a length of said link cables.

18. The device of claim 13, wherein said identification keys connect to one end of said link cables.

19. The device of claim 13, wherein said identification keys are integral to a connection plug of said link cables designed and adapted for connection to said plural plugs.