Testchip design for process analysis in sub-micron DRAM fabrication

• US 5,872,018 A
• Filed: 05/05/1997
• Issued: 02/16/1999
• Est. Priority Date: 05/05/1997
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Vanguard International Semiconductor Corporation
• Inventors: Lee, Daniel Hao-Tien
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US08/851,596
• Time in Patent Office: 652 Days
• Field of Search: 438/17, 438/18, 438/253, 438/396, 438/620
• US Class Current: 438/18
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Integrated circuit chips having large regions of different device density and topography are susceptible to local processing variations which give rise to systematic failures affecting some circuit regions and not others. Over simplified test structures cannot signal these failures during processing. Memory chips have large regions of storage cell arrays serviced by sizeable peripheral regions consisting of logic circuits. The device density and configuration in each of these regions on the chip are quite different. During processing steps these regions present differently to the process agents such as chemical etchants and plasmas producing in local variations of processing rates occur which result in systematic under processing in one region or over processing in another. Memory chips are particularly prone to such variations and also lend themselves well to the design of product specific test structures for flagging these aberrations. Several test structures are described which are formed from regions of the integrated circuit product itself. The structures are designed to monitor specific process steps where such local variations occur. The invention teaches the use of product specific test structures for process monitoring of sub-micron DRAM integrated circuits. The structures described are portions of the cell array outfitted with test probe pads and are capable of measuring opens and shorts in wordlines and bitlines. Another structure comprises a testable string of bitline contacts.

Claims

1. A method for electrical testing of a test structure during the manufacture of a DRAM integrated circuit comprising:

(a) providing a test structure having

(i) a region on a silicon substrate designated for a said test structure;

(ii) field isolation formed in said region in a layout identical to field isolation in a portion of a cell array of said DRAM integrated circuit;

(iii) semiconductive devices formed in said region in a layout identical to said cell array;

(iv) wordlines patterned over said semiconductive devices in a layout identical to that of wordlines in said cell array; and

(v) probe pads formed at the ends of a plurality of said wordlines and located over field oxide in the periphery of said test structure, said plurality of wordlines now becoming testable wordlines, by virtue of their having probe pads at each end, and said testable wordlines further being arranged in groups, each group containing at least three adjacent testable wordlines;

(b) mounting said silicon substrate in a probe testing station;

(c) applying test probes to said probe pads;

(d) measuring resistance between adjacent testable wordlines; and

(e) measuring resistance of each testable wordline.

2. The method of claim 1 wherein said test structure contains between about 50 and 5,000 partially processed memory cells.

3. The method of claim 1 wherein said semiconductive devices are self-aligned polysilicon gate MOSFETs.

4. The method of claim 1 further comprising:

(a) processing said test structure to form

(i) a first insulative layer over said wordlines;

(ii) bitlines patterned over said first insulative layer in a layout identical to identical to that of bitlines in said cell array passing, essentially parallel to each other, from one side of said region to the other and contacting said silicon active area through openings in said first insulative layer; and

(iii) probe pads formed at the ends of a plurality of said bitlines and located over said first insulative layer in the periphery of said structure, said plurality of said bitlines now becoming testable bitlines, by virtue of their having probe pads at each end, and said testable bitlines further being arranged in groups, each group containing at least three adjacent testable bitlines

(b) mounting said silicon substrate on a testing apparatus;

(c) applying test probes to said probe pads;

(d) measuring resistance between adjacent testable bitlines; and

(e) measuring resistance of each testable bitline.

5. The method of claim 4 further comprising:

(a) processing said test structure to form;

(i) a second insulative layer over said second conductive stripes;

(ii) storage capacitors formed over said second insulative layer in a layout identical to corresponding to storage capacitors in said cell array, and contacting active semiconductor regions;

(iii) a third insulative layer over said storage capacitors;

(iv) conductive contacts formed through openings passing through said third insulative layer, said second insulative layer, and first insulative layer, thereby contacting each end of a plurality testable wordlines;

(v) conductive contacts formed through openings passing through said third insulative layer and said second insulative layer, thereby contacting each end of a plurality of testable bitlines;

(vi) conductive contacts formed through openings passing through said third insulative layer, thereby contacting an upper plate of said storage capacitors;

(vii) a conductive contact to said silicon substrate;

(viii) conductive stripes patterned over said second insulative layer and contacting said conductive contacts; and

(ix) probe pads formed at the ends of said conductive stripes and located in the periphery of said structure thereby forming testable wordlines, testable bitlines, and testable cells

(b) mounting said silicon substrate on a testing apparatus;

(c) applying test probes to said probe pads;

(d) measuring resistance between adjacent testable wordlines; and

(e) measuring resistance of each testable wordline;

(f) measuring resistance between adjacent testable bitlines;

(g) measuring resistance of each testable bitline; and

(h) measuring functionality of testable cells.

6. The method of claim 5 wherein said conductive stripes are an aluminum or an aluminum alloy.

7. A method for electrical testing of bitline contacts during the manufacture of a DRAM integrated circuit comprising:

(a) providing a contact string having alternate sections of impurity doped silicon active area and conductive stripes connected by bitline contacts, said contact string further comprising;

(i) a region on a silicon substrate designated for said contact string;

(ii) a linear sequence of islands of impurity doped silicon active area, formed in the framework of said DRAM cell array in said region isolated from one another by field isolation;

(iii) an insulative layer over said silicon active areas;

(iv) openings in said insulative layer exposing portions of said islands of impurity doped silicon active area, said openings arranged to provide two openings over each island in said linear sequence;

(v) bitline contacts formed in said openings;

(vi) a series of conductive stripes, formed in the framework of said DRAM cell array over said insulative layer, said conductive stripes lying astride of said field isolation between said impurity doped silicon active area and forming a conductive path between successive islands through said contacts; and

(vii) probe pads formed at the ends of said contact string and located in the periphery of said region

(b) mounting said silicon substrate in a testing apparatus;

(c) applying test probes to said probe pads; and

(d) measuring the resistance of said contact string.

8. The method of claim 7 wherein said contact string contains between 50 and 5,000 bitline contacts.