Method for etching a semiconductor method for fabricating semiconductor device method for fabricating semiconductor laser and semiconductor laser

• US 5,872,022 A
• Filed: 09/01/1995
• Issued: 02/16/1999
• Est. Priority Date: 09/02/1994
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Kato, Manabu, Takemi, Masayoshi, Motoda, Takashi
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): LEBENTRITT, MICHAEL
• Application Number:
  US08/522,933
• Time in Patent Office: 1,264 Days
• Field of Search: 437/81, 437/105, 437/129, 156/643.1, 156/656.1, 438/39, 438/47, 438/718
• US Class Current: 438/39
• CPC Class Codes: B82Y 20/00 Nanooptics, e.g. quantum optics or photonic crystals
• CPC Class Codes: H01L 21/02392 Phosphides
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02461 Phosphides
• CPC Class Codes: H01L 21/02463 Arsenides
• CPC Class Codes: H01L 21/02543 Phosphides
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/30612 Etching of AIIIBV compounds
• CPC Class Codes: H01S 2304/04 MOCVD or MOVPE
• CPC Class Codes: H01S 5/026 Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers stabilisation of output H01S5/06
• CPC Class Codes: H01S 5/12 the resonator having a periodic structure, e.g. in distributed feedback [DFB] lasers comprising a photonic bandgap structure H01S5/11; surface-emitting lasers H01S5/18
• CPC Class Codes: H01S 5/1228 DFB lasers with a complex coupled grating, e.g. gain or loss coupling
• CPC Class Codes: H01S 5/2077 using lateral bandgap control during growth, e.g. selective growth, mask induced
• CPC Class Codes: H01S 5/2081 using special etching techniques
• CPC Class Codes: H01S 5/2086 lateral etch control, e.g. mask induced
• CPC Class Codes: H01S 5/2232 with inner confining structure between the active layer and the lower electrode
• CPC Class Codes: H01S 5/2237 with a non-planar active layer
• CPC Class Codes: H01S 5/227 Buried mesa structure ; Striped active layer
• CPC Class Codes: H01S 5/2275 : mesa created by etching
• CPC Class Codes: H01S 5/34306 : emitting light at a wavelength longer than 1000nm, e.g. InP based 1300 and 1500nm lasers
• CPC Class Codes: H01S 5/3434 : with a well layer comprising at least both As and P as V-compounds
• CPC Class Codes: H01S 5/4031 : Edge-emitting structures

Abstract

A method of etching a III-V compound semiconductor uses an etching gas including the group V element of the III-V compound semiconductor substrate layer while keeping the III-V compound semiconductor layer at a temperature higher than the crystal growth temperature of the III-V compound semiconductor. Etching using this method provides a higher degree of controllability than wet etching. In addition, because no etching solution is employed, the etching method can be employed in a crystal growth apparatus. Further, because an element of the III-V compound semiconductor layer is employed in the etching gas, incorporation of residual impurities can be prevented, keeping the etched surface clean.

Claims

1. A method of etching a semiconductor comprising etching a III-V compound semiconductor layer using an etching gas including the Group V element of said III-V compound semiconductor layer and excluding etching gases including halogens while keeping said III-V compound semiconductor layer at a temperature higher than a crystal growth temperature of said III-V compound semiconductor layer.

2. The method of claim 1, including adding a gas including the group III element of said III-V compound semiconductor layer to the etching gas to control the etching.

3. The method of claim 1, wherein said III-V compound semiconductor layer is InP and the etching gas includes phosphorus.

4. The method of claim 1, wherein said III-V compound semiconductor layer is InP, including etching said InP layer at a temperature above 700°

C.

5. The method of claim 1, wherein said III-V compound semiconductor layer is InP, including keeping said InP layer at a temperature above 700°

C., using PH₃ gas at a flow rate of 400 SCCM and H₂ at a flow rate of 25 SCCM as etching gases, and keeping the pressure at 30 Torr.

6. The method of claim 1, further comprising:

forming an insulating film with a plurality of stripe-shaped apertures in a plurality of respective regions, each region having apertures of different widths on a surface of said III-V compound semiconductor layer; and

selectively etching said III-V compound semiconductor layer using said insulating film as a mask.

7. The method of claim 1, further comprising:

forming an insulating film with a plurality of stripe-shaped apertures with widths, said film having a plurality of respective regions, each region having apertures of respective, different widths; and

selectively etching said III-V compound semiconductor layer using said insulating film as a mask.

8. A method of etching a semiconductor comprising selectively etching only a region of a surface of a III-V compound semiconductor layer while said III-V compound semiconductor layer is in an ambient of an etching gas including the Group V element of said III-V compound semiconductor layer and excluding etching gases including halogens, and heating said region to a temperature higher than a crystalline growth temperature of said III-V compound semiconductor layer.

9. The method of claim 8, including holding said III-V compound semiconductor layer, during the etching, at a temperature at which crystal growth of said III-V compound semiconductor layer is possible.

10. A method of fabricating a semiconductor device comprising:

forming an insulating film having an aperture on a surface of a III-V compound semiconductor layer;

selectively etching said III-V compound semiconductor layer using said insulating film as a mask using an etching gas including the Group V element of said III-V compound semiconductor layer and excluding etching gases including halogens, while said III-V compound semiconductor layer is maintained at a temperature higher than a crystal growth temperature of said III-V compound semiconductor layer; and

growing another semiconductor layer, using said insulating film as a mask, on said III-V compound semiconductor layer, after replacing the etching gas with a crystal growth gas without said III-V compound semiconductor layer being exposed to air.

11. A method of fabricating a semiconductor device comprising:

forming an insulating film having an aperture on a surface of a first conductivity type III-V compound semiconductor layer;

selectively etching said first conductivity type III-V compound semiconductor layer, using said insulating film as a mask, with an etching gas including the Group V element of said III-V compound semiconductor layer and excluding etching gases including halogens, while maintaining said III-V compound semiconductor layer at a temperature higher than a crystalline growth temperature of said III-V compound semiconductor layer; and

selectively growing a double heterojunction structure comprising a first conductivity type cladding layer, an active layer, and a second conductivity type cladding layer successively, using said insulating film as a mask, after replacing the etching gas with a crystalline growth gas without said III-V compound semiconductor layer being exposed to air.

12. A method of fabricating a semiconductor device comprising:

forming an insulating film having an aperture on a surface of a III-V compound semiconductor layer;

selectively etching said III-V compound semiconductor layers, using said insulating film as a mask, with an etching gas including the Group V element of said III-V compound semiconductor layer and excluding etching gases including halogens, while maintaining said III-V compound semiconductor layer at a temperature higher than a crystalline growth temperature of said III-V compound semiconductor layer; and

selectively growing a multi-quantum well structure layer, using said insulating film as a mask, after replacing the etching gas with a crystalline growth gas without said III-V compound semiconductor layer being exposed to air.

13. A method of fabricating a semiconductor device comprising:

forming an insulating film having a plurality of stripe-shaped apertures arranged in parallel with each other on a III-V compound semiconductor layer; and

selectively etching said III-V compound semiconductor layer, using said insulating film as a mask, with an etching gas including the Group V element of said III-V compound semiconductor layer and excluding etching gases including halogens, while maintaining said III-V compound semiconductor layer at a temperature higher than a crystalline growth temperature of said III-V compound semiconductor layer.

14. The method of fabricating a semiconductor device of claim 13, wherein said insulating film includes a first region in which the stripe-shaped apertures have a first stripe length and a second region including stripe-shaped apertures having different lengths from the first stripe length.

15. The method of fabricating a semiconductor device of claim 13, wherein said plurality of stripes-shaped apertures have a uniform stripe length, and said insulating film has a width in a direction perpendicular to the apertures in a first region that is narrower than the width of said insulating film in a second region.

16. The method of fabricating a semiconductor device of claim 13, comprising after selectively etching said III-V compound semiconductor layer, growing another semiconductor layer using said insulating film as a mask, after replacing the etching gas with a crystal growth gas without said III-V compound semiconductor layer being exposed to air.

17. A method of fabricating a semiconductor layer comprising:

forming a current blocking layer comprising a III-V compound semiconductor on a surface of a first conductivity type III-V compound semiconductor substrate;

forming an insulating film having a stripe-shaped aperture on a surface of said current blocking layer;

forming a stripe-shaped groove by selectively etching said current blocking layer, using said insulating film as a mask, with an etching gas including the Group V element of said III-V compound semiconductor layer and excluding etching gases including halogens, while maintaining said III-V compound semiconductor layer at a temperature higher than a crystalline growth temperature of said III-V compound semiconductor to form a stripe-shaped groove; and

selectively growing a double heterojunction structure comprising a first conductivity type cladding layer, an active layer, and a second conductivity type cladding layer, using said insulating film as a mask, after replacing the etching gas with a crystalline growth gas without the surface of the stripe-shaped groove being exposed to air.

18. A method of fabricating a semiconductor laser comprising:

forming a III-V compound semiconductor double heterojunction structure comprising a first conductivity type cladding layer, an active layer, and a second conductivity type cladding layer on a surface of a first conductivity type III-V semiconductor substrate;

forming a stripe-shaped insulating film double heterojunction structure and forming a mesa stripe by selectively etching said double heterojunction structure to reach said substrate, using said insulating film as a mask and using an etching gas including the Group V element of said III-V compound semiconductor double heterojunction structure and excluding etching gases including halogens, while keeping said III-V compound semiconductor of said double heterojunction structure at a temperature higher than a crystal growth temperature of said III-V compound semiconductor of said double heterojunction structure to form a mesa stripe; and

selectively growing a current blocking layer to bury said mesa stripe, using said insulating film as a mask, after replacing the etching gas with a crystal growth gas without the surface of said stripe-shaped groove being exposed to air.

19. A method of fabricating a semiconductor laser comprising:

forming a current blocking layer comprising a III-V compound semiconductor on a surface of a first conductivity type III-V compound semiconductor substrate;

forming an insulating film having a plurality of stripe-shaped parallel apertures and having different aperture widths on the surface of the current blocking layer;

forming stripe-shaped grooves by selectively etching said current blocking layer to reach said substrate, using said insulating film as a mask, with an etching gas including the Group V element of said III-V compound semiconductor current blocking layer and excluding etching gases including halogens, while maintaining said III-V compound semiconductor current blocking layer at a temperature higher than a crystalline growth temperature of said III-V compound semiconductor, to form a plurality of stripe-shaped grooves; and

selectively growing a double heterojunction structure comprising a first conductivity type cladding layer, a multi-quantum well structure active layer, and a second conductivity type cladding layer, using said insulating film as a mask, after replacing the etching gas with a crystalline growth gas without the surface of the stripe-shaped grooves being exposed to air.

20. A method of fabricating a semiconductor laser device comprising:

forming a first insulating film having a plurality of stripe-shaped parallel apertures and having different aperture widths on a surface of a first conductivity type III-V compound semiconductor substrate;

selectively etching said III-V compound semiconductor substrate, using said first insulating film as a mask, with an etching gas including the Group V element of said III-V compound semiconductor substrate and excluding etching gases including halogens, while maintaining said III-V compound semiconductor substrate at a temperature higher than a crystalline growth temperature of said III-V compound semiconductor substrate, to form a plurality of stripe-shaped grooves;

selectively growing a double heterojunction structure comprising a first conductivity type cladding layer, a multi-quantum well structure active layer, and a second conductivity type cladding layer, using said first insulating film as a mask, after replacing the etching gas with a crystalline growth gas without the surface of the stripe-shaped grooves being exposed to air, to fill the stripe-shaped grooves;

after removing said first insulating film, forming a stripe-shaped second insulating film extending in a length direction of said double heterojunction structure on said double heterojunction structure and etching said double heterojunction structure using said second insulating film as a mask, thereby forming a mesa-stripe; and

forming a current blocking layer burying said mesa-stripe using said second insulating film as a mask.

21. A method of fabricating a semiconductor laser comprising:

forming an insulating film having a stripe-shaped aperture on a surface of a first semiconductor layer comprising a III-V compound semiconductor;

selectively etching said III-V compound semiconductor substrate, using said stripe-shaped insulating film as a mask, with an etching gas including the Group V element of said III-V compound semiconductor layer and excluding etching gases including halogens, while maintaining said III-V compound semiconductor layer at a temperature higher than a crystalline growth temperature of said III-V compound semiconductor, to form a plurality of stripe-shaped grooves;

selectively growing an electron channel layer at the bottom of said stripe-shaped grooves using said insulating film as a growth mask after replacing the etching gas with a crystalline growth gas without the stripe-shaped grooves being exposed to air; and

selectively growing a second III-V compound semiconductor layer comprising the same material as said first semiconductor layer, filling the stripe-shaped grooves using said insulating film as a growth mask.

22. A method of fabricating a semiconductor device comprising:

forming an electron channel layer comprising an intrinsic semiconductor layer and a second semiconductor layer comprising an intrinsic III-V compound semiconductor layer electron channel layer on a surface of a first semiconductor layer;

forming an insulating film having a stripe-shaped aperture on a surface of said second semiconductor layer;

etching said second semiconductor layer, using said insulating film as a mask, with an etching gas including the Group V element of said III-V compound semiconductor layer and excluding etching gases including halogens, while maintaining said III-V compound semiconductor layer at a temperature higher than a crystal growth temperature of said III-V compound semiconductor, to a depth not reaching said electron channel layer, to form a stripe-shaped V-shaped groove; and

selectively growing a third III-V compound semiconductor layer having a prescribed conductivity type and comprising the same material as said first semiconductor layer to fill the V-shaped groove using said insulating film as a mask, after replacing the etching gas with a crystalline growth gas without the surface of said second semiconductor layer being exposed to air.