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Method for stacked three dimensional device manufacture

  • US 5,872,025 A
  • Filed: 03/11/1997
  • Issued: 02/16/1999
  • Est. Priority Date: 07/26/1995
  • Status: Expired due to Fees
First Claim
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1. A method of forming a plurality of semiconductor chip stacks comprising the steps of:

  • providing a plurality of wafers each having a plurality of chip regions formed therein each of which are surrounded by chip separation regions;

    joining said plurality of wafers together to form a wafer stack with said chip regions and chip separation regions on said wafers in said wafer stack being in alignment; and

    thenseparating a plurality of stacks of chips from said wafer stack, each of said plurality of stacks of chips being comprised of a plurality of chips arranged in a stack, each of said plurality of chips being formed from individual chip regions of said plurality of chip regions in each wafer, said step of separating causing a separation of a stack of chips from said wafer stack at said chip separation regions which are aligned during said joining step wherein said chip separation regions in said wafer are comprised of insulator filled trenches.

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