Method for stacked three dimensional device manufacture
First Claim
1. A method of forming a plurality of semiconductor chip stacks comprising the steps of:
- providing a plurality of wafers each having a plurality of chip regions formed therein each of which are surrounded by chip separation regions;
joining said plurality of wafers together to form a wafer stack with said chip regions and chip separation regions on said wafers in said wafer stack being in alignment; and
thenseparating a plurality of stacks of chips from said wafer stack, each of said plurality of stacks of chips being comprised of a plurality of chips arranged in a stack, each of said plurality of chips being formed from individual chip regions of said plurality of chip regions in each wafer, said step of separating causing a separation of a stack of chips from said wafer stack at said chip separation regions which are aligned during said joining step wherein said chip separation regions in said wafer are comprised of insulator filled trenches.
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Abstract
Stacked three-dimensional devices can be prepared by stacking wafers as an alternative to stacking individual devices. Chip regions are formed on several wafers with each chip region being surrounded by a separation region, such as an insulator filled trench. The wafers are then stacked with the chip regions in alignment. Aligning the wafers can be facilitated using notched regions in the periphery of the wafers. The wafers are then joined together by lamination. After laminating the stacks of wafers, stacks of chips are separated by etching, dicing or other processes, which separate out stacked chip devices from the stacked wafer at the chip separation regions. The process allows several stacked chip devices to be manufactured simultaneously.
102 Citations
12 Claims
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1. A method of forming a plurality of semiconductor chip stacks comprising the steps of:
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providing a plurality of wafers each having a plurality of chip regions formed therein each of which are surrounded by chip separation regions; joining said plurality of wafers together to form a wafer stack with said chip regions and chip separation regions on said wafers in said wafer stack being in alignment; and
thenseparating a plurality of stacks of chips from said wafer stack, each of said plurality of stacks of chips being comprised of a plurality of chips arranged in a stack, each of said plurality of chips being formed from individual chip regions of said plurality of chip regions in each wafer, said step of separating causing a separation of a stack of chips from said wafer stack at said chip separation regions which are aligned during said joining step wherein said chip separation regions in said wafer are comprised of insulator filled trenches. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method comprising the steps of:
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providing a plurality of wafers each having a plurality of circuit areas thereon, each of the wafers having a frontside and a backside, and each of the circuit areas surrounded by an oxide-filled trench; depositing an adhesive onto the backside of at least one of the circuits areas; laminating with the adhesive the plurality of wafers frontside to backside; and separating a stack of the circuit areas formed by the laminating step including removing oxide surrounding the circuit areas in the stack. - View Dependent Claims (12)
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Specification