High aspect ratio gapfill process by using HDP

• US 5,872,058 A
• Filed: 06/17/1997
• Issued: 02/16/1999
• Est. Priority Date: 06/17/1997
• Status: Expired due to Term

• Current Assignee: Novellus Systems Incorporated (LAM Research Corporation)
• Original Assignee: Novellus Systems Incorporated (LAM Research Corporation)
• Inventors: Mountsier, Thomas W., Van Cleemput, Patrick A.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): LEBENTRITT, MICHAEL
• Application Number:
  US08/876,949
• Time in Patent Office: 609 Days
• Field of Search: 438/692, 438/732, 438/733, 438/787, 438/788
• US Class Current: 438/692
• CPC Class Codes: C23C 16/045 Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
• CPC Class Codes: C23C 16/402 Silicon dioxide
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/31612 on a silicon body
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76837 Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics

Abstract

A process for filling high aspect ratio gaps on substrates uses conventional high density plasma deposition processes while reducing the concentration of the inert gas, such as Ar, to 0-13% of the total process gas flow. By reducing the inert gas concentration, sputtering or etching is reduced, resulting in reduced sidewall deposition from the sputtered material. Consequently, gaps with aspect ratios of 3.0:1 and higher can be filled without the formation of voids and without damaging circuit elements.

Claims

1. A process for filling gaps during integrated circuit production, comprising the steps of:

providing a gas mixture comprised of silicon-containing, oxygen-containing, and inert components, wherein said inert components comprise no more than 13% total concentration of said gas mixture; and

depositing a film over said gaps by using said gas mixture for simultaneous CVD and sputter etching.

2. The process of claim 1, wherein said silicon-containing component is silane.

3. The process of claim 1, wherein said oxygen-containing component is O₂ .

4. The process of claim 1, wherein said inert component is selected from the group consisting of argon, helium and hydrogen.

5. The process of claim 1, wherein said gas mixture is at a pressure between 1 and 3 mTorr.

6. The process of claim 5, wherein said gas mixture is at a pressure of 2 mTorr.

7. The process of claim 2, wherein said silane is at a flow rate of 80 to 250 sccm.

8. The process of claim 3, wherein said O₂ is at a flow rate of 120 to 250 sccm.

9. The process of claim 4, wherein said inert component is argon at a flow rate of 0 to 50 sccm.

10. A process for filling gaps during integrated circuit production, comprising the step of:

depositing a film over said gaps by HDP deposition using a gas mixture comprised of silicon-containing, oxygen-containing, and inert components, wherein said inert components comprise no more than 13% total concentration of said gas mixture.