Hexagonal sense cell architecture

• US 5,872,380 A
• Filed: 08/21/1995
• Issued: 02/16/1999
• Est. Priority Date: 11/02/1994
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Andreev, Alexander E., Kudryavtsev, Valerity B., Scepanovic, Ranko, Kapoor, Ashok K., Koford, James S., Aleshin, Stanislav V., Rostoker, Michael D., Podkolzin, Alexander S., Jones, Edwin R., Padmanahben, Gobi R.
• Primary Examiner(s): WHITEHEAD JR, CARL W
• Application Number:
  US08/517,189
• Time in Patent Office: 1,275 Days
• Field of Search: 257/202, 257/206, 257/208, 257/210, 257/368, 257/369, 257/341, 257/351, 257/371, 257/379, 257/390, 257/391, 257/393, 257/401, 257/408, 257/1, 326/38, 327/563
• US Class Current: 257/369
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 19/09441 of the same canal type
• CPC Class Codes: H03K 19/0948 using CMOS or complementary insulated gate field-effect transistors
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices

Abstract

Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arrangement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60°. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a "tri-ister" is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.

Claims

1. A sense cell, comprising:

a triangular structure fabricated on a semiconductor substrate;

a first transistor formed as part of the triangular structure, the first transistor having a source region formed at one coner of the triangular structure, the source region of the first transistor being connected to ground, the first transistor having a gate electrode connected to a voltage V_G3 ;

a second transistor formed as part of the triangular structure, the second transistor having a drain region formed at one coner of the triangular structure, the drain region of the second transistor being connected to a first end of a first resistor, the first resistor having a second end connected to voltage V_DD, the second transistor having a gate electrode connected to a voltage V₁ ;

a third transistor formed as part of the triangular structure, the third transistor having a drain region formed at one coner of the triangular structure, the drain region of the third transistor being connected to a first end of a second resistor, the second resistor having a second end connected to voltage V_DD, the third transistor having a gate electrode connected to a voltage V₂ ; and

,

the first transistor, the second transistor, and the third transistor having a common source-drain region.

2. An amplifier structure, comprising:

a semiconductor substrate including a triangular doped region having a central common region, and first, second and third regions adjacent to first, second and third vertices of the doped region respectively;

first, second and third gates formed between the first, second and third regions respectively and the common region;

a first resistance having a first end connected to the first region; and

a second resistance having a first end connected to the second region.

3. A structure as in claim 2, in which:

the first and second resistances have second ends that are opposite to the first ends thereof respectively; and

the structure further comprises;

first means for connecting the second ends of the first and second resistances to a first electrical potential; and

second means for connecting the third region to a second electrical potential which is different from the first electrical potential.

4. A structure as in claim 3, further comprising interconnect wiring which is electrically connected to the first, second and third gates, to the second ends of the first and second resistances, and to the third region in a predetermined manner, the interconnect wiring extending in three directions that are angularly displaced from each other by 60°

.

5. A structure as in claim 3, further comprising third means for applying a control signal to the third gate.

6. A structure as in claim 5, further comprising fourth means for applying an input signal to the first gate and a reference potential to the second gate.

7. A structure as in claim 5, further comprising fourth means for applying a differential input signal across the first and second gates.

8. A sense amplifier for a memory cell which has an output, comprising:

a semiconductor substrate including a triangular doped region having a central common region, and first, second and third regions adjacent to first, second and third vertices of the doped region respectively;

first, second and third gates formed between the first, second and third regions respectively and the common region;

a first resistance connected between the first region and a first electrical potential;

a second resistance connected between the second region and the first electrical potential; and

means for applying a control signal to the third gate;

in which;

the third region is connected to a second electrical potential that is different from the first electrical potential; and

at least one of the first and second gates is connected to said output of the memory cell.

9. An amplifier as in claim 8, further comprising interconnect wiring which is electrically connected to the first, second and third gates, to external ends of the first and second resistances, and to the third region in a predetermined manner, the interconnect wiring extending in three directions that are angularly displaced from each other by 60°

.

10. An amplifier as in claim 8, in which said output of the memory cell is connected to the first gate and a reference potential is applied to the second gate.

11. An amplifier as in claim 8, in which said output of the memory cell is a differential output and is applied across the first and second gates.

12. A microelectronic integrated circuit memory, comprising:

a semiconductor substrate; and

a plurality of memory devices formed on the substrate, at least one of said memory devices comprising a triangular memory cell having an output, and a sense amplifier for amplifying said output, the sense amplifier including;

a triangular doped region having a central common region, and first, second and third regions adjacent to first, second and third vertices of the doped region respectively;

first, second and third gates formed between the first, second and third regions respectively and the common region;

a first resistance connected between the first region and a first electrical potential;

a second resistance connected between the second region and the first electrical potential; and

means for applying a control signal to the third gate;

in which;

the third region is connected to a second electrical potential that is different from the first electrical potential; and

at least one of the first and second gates is connected to said output of the memory cell.

13. A memory as in claim 12, further comprising interconnect wiring which is electrically connected to the first, second and third gates, to external ends of the first and second resistances, and to the third region in a predetermined manner, the interconnect wiring extending in three directions that are angularly displaced from each other by 60°

.

14. A memory as in claim 12, in which said output of the memory cell is connected to the first gate and a reference potential is applied to the second gate.

15. A memory as in claim 12, in which said output of the memory cell is a differential output and is applied across the first and second gates.

16. A memory as in claim 12, in which the memory cell and the sense amplifier are closely packed with additional memory cells and sense amplifiers on the substrate.

17. A memory as in claim 16, in which the memory cell and the sense amplifier, and the additional memory cells and the additional sense amplifiers define a hexagonal shape.

18. An electronic system comprising an integrated circuit memory, and additional electronic elements that are operatively connected to the memory, the memory including:

a semiconductor substrate; and

a plurality of memory devices formed on the substrate, at least one of said memory devices comprising a triangular memory cell having an output, and a sense amplifier for amplifying said output, the sense amplifier including;

a triangular doped region having a central common region, and first, second and third regions adjacent to first, second and third vertices of the doped region respectively;

first, second and third gates formed between the first, second and third regions respectively and the common region;

a first resistance connected between the first region and a first electrical potential;

a second resistance connected between the second region and the first electrical potential; and

means for applying a control signal to the third gate;

in which;

the third region is connected to a second electrical potential that is different from the first electrical potential; and

at least one of the first and second gates is connected to said output of the memory cell.

19. A system as in claim 18, in which the memory comprises a Single-Chip Module (SCM).

20. A system as in claim 18, comprising a Multi-Chip Module (MCM), the memory being part of the MCM.

21. A system as in claim 18, further comprising a Board-Level Product (BLP) including a circuit board on which the memory is mounted.

22. A system as in claim 18, further comprising a box level product including a power supply for the memory.

23. A system as in claim 18, further comprising interconnect wiring which is electrically connected to the first, second and third gates, to external ends of the first and second resistances, and to the third region in a predetermined manner, the interconnect wiring extending in three directions that are angularly displaced from each other by 60°

.

24. A system as in claim 18, in which said output of the memory cell is connected to the first gate and a reference potential is applied to the second gate.

25. A system as in claim 18, in which said output of the memory cell is a differential output and is applied across the first and second gates.

26. A system as in claim 18, in which the memory cell and the sense amplifier are closely packed with additional memory cells and sense amplifiers on the substrate.

27. A system as in claim 26, in which the memory cell and the sense amplifier, and the additional memory cells and the additional sense amplifiers define a hexagonal shape.