Low voltage CMOS analog multiplier with extended input dynamic range

• US 5,872,446 A
• Filed: 08/12/1997
• Issued: 02/16/1999
• Est. Priority Date: 08/12/1997
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: McElwee, James Francis Jr., Gyurcsik, Ronald Steven, Cranford, Hayden Clavie Jr.
• Primary Examiner(s): NGUYEN, MATTHEW VAN
• Application Number:
  US08/910,165
• Time in Patent Office: 553 Days
• Field of Search: 323/312, 323/313, 323/315, 327/538, 327/539, 327/543, 330/257, 330/288
• US Class Current: 323/315
• CPC Class Codes: G05F 3/247 producing a voltage or current as a predetermined function of the supply voltage
• CPC Class Codes: H03D 2200/0033 Current mirrors
• CPC Class Codes: H03D 2200/0043 Bias and operating point
• CPC Class Codes: H03D 2200/0084 Lowering the supply voltage and saving power
• CPC Class Codes: H03D 7/1441 using field-effect transistors H03D7/145 takes precedence
• CPC Class Codes: H03D 7/1458 Double balanced arrangements, i.e. where both input signals are differential
• CPC Class Codes: H03D 7/1491 Arrangements to linearise a transconductance stage of a mixer arrangement
• CPC Class Codes: H03G 1/0023 in emitter-coupled or cascode amplifiers H03G1/0029 takes precedence

Abstract

A low voltage CMOS multiplier uses a transconductance stage to generate a dynamic bias current which is used to compensate for non-linear terms in a Gilbert Cell multiplier circuit. Common mode dependence is minimized by using balanced differential input stages for both the transconductance and multiplier stages.

Claims

1. A circuit for multiplying two signals represented by two analog voltages V_x and V_y comprising:

a transconductance circuit responsive to V_x for converting V_x to a related first current (I_tran); and

,

a Gilbert Cell core multiplier having two n-channel cross coupled differential transistor pairs responsive to said voltage V_x and providing a second current (I_x, I_y) related to the value of V_x, a folded p-channel transistor pair responsive to the voltage V_y and providing a third current (I_y1, I_y2) related to the voltage V_y, and a current source (M14,M15) under control of said first current for combining said second and third currents whereby the voltage output (V_out) of the said Gibert Cell core is a linear representation of the product of V_x and V_y.

2. The multiplier set forth in claim 1 in which the signal voltage V_x is a differential voltage (V_x+ and V_x-) and the transconductance circuit responsive to the differential voltage includes:

a first pair of transistors (M3 and M4) each responsive to a different phase of the differential signal voltage;

a second pair of transistors (M1 and M2) each responsive to a different phase of the differential signal voltage;

said first pair being scaled by a size factor n relative to the second pair; and

,

circuit means including a current source for connecting the two pairs between a bias voltage and ground.

3. The multiplier circuit set forth in claim 2 in which the transconductance coefficients of the transistors in the transconductance circuit are set equal to a predetermined ratio of the transconductance coefficients of the transistors in the Gilbert Cell.

4. The multiplier circuit set forth in claim 3 in which the predetermined ratio is one.

5. The multiplier set forth in claim 4 in which the scale factor n is set equal to 1+2/√

3.