Input buffer with stabilized trip points

• US 5,872,464 A
• Filed: 08/12/1996
• Issued: 02/16/1999
• Est. Priority Date: 08/12/1996
• Status: Expired due to Term

• Current Assignee: Callahan Cellular LLC (Intellectual Ventures LLC)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Gradinariu, Julian C.
• Primary Examiner(s): SANTAMAURO, JON P
• Application Number:
  US08/696,008
• Time in Patent Office: 918 Days
• Field of Search: 326/21, 326/68, 326/31-34, 326/71, 326/121, 326/82-83, 327/530, 327/538
• US Class Current: 326/71
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS

Abstract

The present invention provides a circuit and method using a floating PMOS transistor connected in series between the transistors of an input invertor. The floating PMOS transistor may be used to control the amount of current through the transistors. The gate of the floating PMOS transistor may be connected through a reference line to a duplicate of the input inverter stage. The duplicate stage is generally located in a reference block and fed with a stabilized reference voltage. Each couple (formed by the buffers input stage and the duplicate stage) functions as a differential comparator, which checks the input voltage against the reference voltage and rejects the power supply voltage variations which are perceived as a common-mode noise signal. The supply current is fixed by the reference voltage which reduces power consumption at high input voltages and high supply voltages.

Claims

1. A circuit comprising:

a first circuit comprising a first transistor, a second transistor coupled to said first transistor, and a third transistor coupled to said second transistor, said first circuit configured to provide a first reference signal in response to a reference voltage and a first supply voltage;

a second circuit configured to provide a second reference signal in response to said first supply voltage, a second supply voltage and an input voltage, said second circuit comprising a fourth transistor, a fifth transistor and a sixth transistor, wherein each of said fourth transistor and said fifth transistor receives said input voltage, said fourth transistor is coupled to each of said first supply voltage and a first source/drain terminal of said sixth transistor, said fifth transistor is coupled to each of said second supply voltage and a second source/drain terminal of said sixth transistor, and a gate of said sixth transistor receives said first reference signal; and

a third circuit configured to provide an output signal in response to said first and second reference signals.

2. The circuit according to claim 1 wherein said second circuit further comprises a plurality of transistors coupled to each other.

3. The circuit according to claim 1 further comprising a fourth circuit configured to generate said reference voltage.

4. The circuit according to claim 3 wherein said fourth circuit comprises a plurality of transistors coupled to each other.

5. An input buffer comprising the circuit of claim 1.

6. A static random access memory (SRAM) comprising the input buffer of claim 5.

7. An input buffer comprising a plurality of circuits according to claim 1.

8. The input buffer according to claim 7 further comprising an input buffer output provided in response to a cascaded combination of each of said output signals.

9. The circuit according to claim 4 wherein said fourth and fifth transistors comprise PMOS transistors and said sixth transistor comprises an NMOS transistor.

10. The input buffer circuit of claim 1, wherein said first transistor receives said reference voltage and is coupled to each of said first supply voltage, a first source/drain terminal of said second transistor and a gate of said second transistor.

11. The input buffer of circuit of claim 10, wherein said third transistor receives said reference voltage and is coupled to each of said second supply voltage and a second source/drain terminal of said second transistor.

12. The input buffer circuit of claim 10, wherein said second circuit comprises a fourth transistor, a fifth transistor and a sixth transistor, each of said fourth transistor and said fifth transistor receives said input signal, said fourth transistor is coupled to each of said first supply voltage and a first source/drain terminal of said sixth transistor, said fifth transistor is coupled to each of a second supply voltage and a second source/drain terminal of said sixth transistor, and a gate of said sixth transistor receives said reference signal.

13. The input buffer circuit of claim 11, wherein said second circuit comprises a fourth transistor, a fifth transistor and a sixth transistor, each of said fourth transistor and said fifth transistor receives said input signal, said fourth transistor is coupled to each of said first supply voltage and a first source/drain terminal of said sixth transistor, said fifth transistor is coupled to each of a second supply voltage and a second source/drain terminal of said sixth transistor, and a gate of said sixth transistor receives said reference signal.

14. An input buffer circuit comprising:

a first circuit comprising (i) a first transistor that receives a reference voltage and is coupled to a first supply voltage, (ii) a second transistor having a first source/drain terminal and a gate coupled to said first transistor, and (iii) a third transistor that receives said reference voltage and is coupled to each of a second supply voltage and a second source/drain terminal of said second transistor, said first circuit configured to generate said reference signal in response to a reference voltage and said first supply voltage; and

a second circuit configured to generate an output signal in response to said reference signal, a second supply voltage and an input signal, said first and second supply voltages being the same or different.

15. The circuit according to claim 14 wherein said first circuit further comprises a fourth transistor, a fifth transistor and a sixth transistor coupled to each other.

16. The input buffer circuit according to claim 14 wherein said second circuit further comprising a fourth transistor, a fifth transistor coupled to said fourth transistor and a sixth transistor coupled to said fifth transistor, at least one of said fourth transistor and said sixth transistor receiving said input signal and being coupled to one of said first and second supply voltages.

17. The input buffer according to claim 14 further comprising an inverter configured to generate an output in response to said output signal.

18. A static random access memory (SRAM) comprising the input buffer of claim 14.

19. The input buffer circuit of claim 16, wherein each of said fourth transistor and said fifth transistor receives said input signal, said fourth transistor is coupled to each of said first supply voltage and a first source/drain terminal of said sixth transistor, said fifth transistor is coupled to each of said second supply voltage and a second source/drain terminal of said sixth transistor, and a gate of said sixth transistor receives said reference signal.

20. A method for improving the response time of an input buffer comprising:

generating a first reference signal from first and second PMOS transistors and an NMOS transistor in response to a reference voltage and a supply voltage, wherein said first PMOS transistor receives said reference voltage and is coupled to each of said supply voltage, a first source/drain terminal of said second PMOS transistor and a gate of said second PMOS transistor and said NMOS transistor receives said reference voltage and is coupled to each of said supply voltage and a second source/drain terminal of said second PMOS transistor;

generating a second reference signal in response to said first reference signal, said supply voltage and an input voltage; and

generating an output signal in response to said first and second reference signal.

21. The method according to claim 20 further comprising:

generating said second reference signal in response to (i) a second NMOS transistor and (ii) third and fourth PMOS transistors.

22. The method of claim 21, wherein each of said fifth and third PMOS transistors is coupled to said first supply voltage, and each of said second and fourth PMOS transistors receives said reference signal.