Identification and/or sensor system

• US 5,872,520 A
• Filed: 10/24/1996
• Issued: 02/16/1999
• Est. Priority Date: 10/24/1995
• Status: Expired due to Term

• Current Assignee: Epcos AG (TDK Corporation)
• Original Assignee: Siemens AG
• Inventors: Ostermayer, Gerald, Pohl, Alfred, Seifert, Franz
• Primary Examiner(s): Horabik, Michael
• Assistant Examiner(s): JEANGLAUDE, JEAN BRUNER
• Application Number:
  US08/736,371
• Time in Patent Office: 845 Days
• Field of Search: 340/825.34, 340/572, 331/18, 331/25, 331/17, 331/1 A, 331/DIG. 2, 331/27, 331/16, 375/373, 375/376, 327/2, 329/323, 329/325, 329/50, 325/320, 325/419
• US Class Current: 340/5.61
• CPC Class Codes: G01S 13/751 wherein the responder or reflector radiates a coded signal
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs

Abstract

An identification and/or sensor system includes a sensor that queries an identification and/or sensor configuration which contains resonators. A receiver receives an answer signal from the identification and/or sensor configuration. The receiver includes a phase-locked loop for converting a resonator decay signal into a signal of constant frequency and constant envelope curve.

Claims

1. An identification and/or sensor system, comprising:

a transmitter sending query signals by radio;

an identification and/or sensor configuration receiving the query signals, sending answer signals and having resonators for defining at least one parameter to be queried;

a receiver evaluating the answer signals sent back by said identification and/or sensor configuration, said receiver having a scanned phase-locked loop triggered by the answer signal, said phase-locked loop having a sample and hold circuit, and said receiver having a threshold value detector triggering said sample and hold circuit;

said phase-locked loop also having a phase detector, a reversing switch downstream of said sample and hold circuit, a voltage-controlled oscillator and a loop filter having an output coupled through said sample and hold circuit to said voltage-controlled oscillator and coupled directly through said reversing switch to said voltage-controlled oscillator; and

said threshold value detector is an asynchronous detector furnishing two threshold value output signals for variously high input signal levels, one of the output signals represents a high input signal level and couples said sample and hold circuit to an output of said phase detector, and another of the output signals represents a low input signal level coupling said loop filter to the output of said phase detector, directly through said reversing switch or through said sample and hold circuit.

2. The identification and/or sensor system according to claim 1, including a counter coupled to an output of said phase-locked loop.

3. The identification and/or sensor system according to claim 2, including a computer connected to said counter, and a synthesizer controlled by said computer as a function of frequency information furnished by said counter, said synthesizer being connected to said mixer for delivering a signal to be mixed with the query signal.

4. The identification and/or sensor system according to claim 1, including a mixer connected upstream of said phase-locked loop.

5. The identification and/or sensor system according to claim 4, including a computer, and a synthesizer controlled by said computer and connected to said mixer for delivering a signal to be mixed with the query signal.

6. The identification and/or sensor system according to claim 5, wherein said computer adjusts a frequency of the query signal in said transmitter.

7. The identification and/or sensor system according to claim 1, wherein said phase detector is a ring mixer with a phase detector constant defined by a product of amplitudes of the input signal and of a signal of said voltage-controlled oscillator.

8. The identification and/or sensor system according to claim 1, including a stage connected upstream of said phase-locked loop for keeping an amplitude of a phase-locked loop input signal constant.

9. The identification and/or sensor system according to claim 8, wherein said stage for keeping the amplitude constant is limiter amplifier.

10. The identification and/or sensor system according to claim 8, wherein said stage for keeping the amplitude constant is a logarithmic amplifier.

18. The identification and/or sensor system according to claim 1, wherein said phase-locked loop is a digital closed control loop.

19. The identification and/or sensor system according to claim 18, wherein said phase-locked loop has a numerical controlled oscillator and further components, and including a control computer in which said further components of said phase-locked loop and control functions are integrated.

11. An identification and/or sensor system, comprising:

a transmitter sending query signals by radio;

an identification and/or sensor configuration receiving the query signals, sending answer signals and having resonators for defining at least one parameter to be queried;

a receiver evaluating the answer signals sent back by said identification and/or sensor configuration, said receiver having a scanned phase-locked loop triggered by the answer signal, said phase-locked loop having a sample and hold circuit, and said receiver having a threshold value detector triggering said sample and hold circuit; and

a reversing switch, another phase-locked loop with a sample and hold circuit, said two phase-locked loops having outputs coupled to said reversing switch, a sample control circuit downstream of said threshold value detector for furnishing two sample control signals for triggering said sample and hold circuits, and the output signal of one of said phase-locked loops triggering said reversing switch.

12. An identification and/or sensor system, comprising:

a transmitter sending query signals by radio;

an identification and/or sensor configuration receiving the query signals, sending answer signals and having resonators for defining at least one parameter to be queried;

a receiver evaluating the answer signals sent back by said identification and/or sensor configuration, said receiver having a scanned phase-locked loop triggered by the answer signal, said phase-locked loop having a sample and hold circuit, and said receiver having a threshold value detector triggering said sample and hold circuit; and

a transmit/receive switch, a shunt branch connected parallel to said transmit/receive switch, and a computer controlling said transmit/receive switch and said shunt branch, said phase-locked loop having a phase detector and a single voltage-controlled oscillator belonging to both said transmitter and said receiver, said voltage-controlled oscillator having an output coupled through said transmit/receive switch and through said shunt branch to said phase detector.

13. The identification and/or sensor system according to claim 12, wherein said shunt branch includes a shunt switch, a phase correction circuit coupled to said shunt switch, and a damping circuit coupled to said phase correction circuit.

14. The identification and/or sensor system according to claim 12, including an amplifier coupling said voltage-controlled oscillator to said transmit/receive reversing switch and to said shunt branch.

15. The identification and/or sensor system according to claim 12, wherein said shunt branch is a further phase-locked loop.

16. The identification and/or sensor system according to claim 12, including a detector circuit triggered by said phase detector in said phase-locked loop for detecting a locked-in state of said phase-locked loop, and a signal generator triggered by said detector circuit for varying a frequency of said voltage-controlled oscillator, said voltage-controlled oscillator being turned off by said detector circuit upon detection of the locked-in state of said phase-locked loop.

17. The identification and/or sensor system according to claim 16, including a loop filter connected upstream of said detector circuit.