Sense amplifier for low read-voltage memory cells

• US 5,872,739 A
• Filed: 04/17/1997
• Issued: 02/16/1999
• Est. Priority Date: 04/17/1997
• Status: Expired due to Term

• Current Assignee: Radiant Technologies, Inc. (Salesforce.com, Inc.)
• Original Assignee: Radiant Technologies, Inc. (Salesforce.com, Inc.)
• Inventors: Womack, Richard
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US08/841,905
• Time in Patent Office: 670 Days
• Field of Search: 365/207, 365/205, 365/189.07, 365/145, 365/210
• US Class Current: 365/207
• CPC Class Codes: G11C 11/2273 Reading or sensing circuits or methods
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

A sense amplifier for comparing the resistance of a reference cell connected to a reference bit line to the resistance of a data cell connected to a data bit line. The amplifier includes a first terminal for connecting the sense amplifier to the reference bit line and a second terminal for connecting the sense amplifier to the data bit line. A reference current to voltage amplifier is connected to the first terminal for generating a reference voltage related to the current flowing through the reference bit line and for maintaining the first terminal at a reference potential when the current flowing through the reference bit line is less than a first current value. A data current to voltage amplifier is connected to the second terminal for generating a data voltage related to the current flowing through the data bit line and for maintaining the second terminal at the reference potential when the current flowing through the data bit line is less than a second current value. A comparitor compares the reference and data voltages. The data current to voltage amplifier includes an operational amplifier for measuring the difference between a potential on a first conductor and the potential on the data bit line. The operational amplifier allows the reference potential to be set at a lower voltage than is available in prior art designs. The invention utilizes a capacitive dividing scheme for pre-charging the bit lines prior to connecting the sense amplifier.

Claims

1. A sense amplifier for comparing the resistance of a reference cell connected to a reference bit line to the resistance of a data cell connected to a data bit line, said amplifier comprising:

a first terminal for connecting said sense amplifier to said reference bit line;

a second terminal for connecting said sense amplifier to said data bit line;

a reference current to voltage amplifier for generating a reference voltage related to the current flowing through said reference bit line and for maintaining said first terminal at a reference potential during the comparison of said resistance of said reference cell with the resistance of said data cell;

a data current to voltage amplifier for generating a data voltage related to the current flowing through said data bit line and for maintaining said second terminal at said reference potential during the comparison of said resistance of said reference cell with said resistance of said data cell; and

a comparitor for comparing said reference and data voltages, wherein said data current to voltage amplifier comprises an operational amplifier for measuring the difference between a potential on a conductor and the potential on said data bit line.

2. A sense amplifier for comparing the resistance of a reference cell connected to a reference bit line to the resistance of a data cell connected to a data bit line, said amplifier comprising:

a first terminal for connecting said sense amplifier to said reference bit line;

a second terminal for connecting said sense amplifier to said data bit line;

a reference current to voltage amplifier for generating a reference voltage related to the current flowing through said reference bit line and for maintaining said first terminal at a reference potential during the comparison of said resistance of said reference cell with the resistance of said data;

a data current to voltage amplifier for generating a data voltage related to the current flowing through said data bit line and for maintaining said second terminal at said reference potential during the comparison of said resistance of said reference cell with said resistance of said data;

a comparitor for comparing said reference and data voltages, wherein said data current to voltage amplifier comprises an operational amplifier for measuring the difference between a potential on a conductor and the potential on said data bit line; and

a precharge circuit for connecting each of said bit lines to ground and said conductor to a precharge voltage, Vc, in response to a first control signal and for connecting said conductor to said bit lines in response to a second control signal, wherein said reference potential is equal to Vc*(C1/(C1+C2)) wherein C1 is the capacitance of said conductor and C2 is the sum of the capacitances of all bit lines connected to said sense amplifier.

3. In a memory having a plurality of bit lines connected to a sense amplifier, a method for precharging said bit lines to a reference potential, said method comprising the steps of

connecting a conductor having a capacitance C1 to a terminal having a voltage Vc and connecting said bit lines to a terminal at a potential Vb and then connecting said bit lines to said conductor wherein Vc, Vb, and C1 are chosen such that said reference potential is equal to Vb+(Vc-Vb)*(C1/(C1+C2)) wherein C1 is the capacitance of said conductor and C2 is the sum of the capacitances of said bit lines.