High speed single chip digital video network apparatus

• US 5,872,784 A
• Filed: 03/28/1995
• Issued: 02/16/1999
• Est. Priority Date: 10/20/1993
• Status: Expired due to Term

• Current Assignee: LSI Corporation (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Desai, Sanjay, Rostoker, Michael D., Daane, John P., Stelliga, D. Tony
• Primary Examiner(s): HSU, ALPUS
• Application Number:
  US08/412,862
• Time in Patent Office: 1,421 Days
• Field of Search: 348/7, 348/12, 348/13, 348/14, 348/16, 348/17, 348/19, 348/384, 348/423, 348/426, 348/441, 348/461, 348/465, 348/469, 364/514 R, 364/514 A, 364/514 C, 370/357, 370/360, 370/395, 370/396, 370/400, 370/401, 370/402, 370/403, 370/404, 370/405, 370/406, 370/407, 370/408, 370/410, 370/419, 370/420, 370/421, 370/428, 370/465 , 370/466, 370/467, 370/471, 370/474, 370/522
• US Class Current: 370/395.64
• CPC Class Codes: G06F 13/128 for dedicated transfers to a network for protocol converters G06F13/387
• CPC Class Codes: G10L 19/00 Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis in musical instruments G10H
• CPC Class Codes: H04L 12/5602 Bandwidth control in ATM Networks, e.g. leaky bucket
• CPC Class Codes: H04L 2012/5613 Bus (including DQDB)
• CPC Class Codes: H04L 2012/5614 User Network Interface
• CPC Class Codes: H04L 2012/5616 Terminal equipment, e.g. codecs, synch.
• CPC Class Codes: H04L 2012/5632 Bandwidth allocation
• CPC Class Codes: H04L 2012/5635 Backpressure, e.g. for ABR
• CPC Class Codes: H04L 2012/5636 Monitoring or policing, e.g. compliance with allocated rate, corrective actions
• CPC Class Codes: H04L 2012/5637 Leaky Buckets
• CPC Class Codes: H04L 2012/5638 Services, e.g. multimedia, GOS, QOS
• CPC Class Codes: H04L 2012/5652 Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
• CPC Class Codes: H04L 2012/5653 using the ATM adaptation layer [AAL]
• CPC Class Codes: H04L 2012/5664 Support of Video, e.g. MPEG
• CPC Class Codes: H04L 45/745 Address table lookup; Address filtering
• CPC Class Codes: H04L 49/25 Routing or path finding in a switch fabric
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/3081 ATM peripheral units, e.g. policing, insertion or extraction
• CPC Class Codes: H04L 49/355 Application aware switches, e.g. for HTTP
• CPC Class Codes: H04L 49/505 Corrective measures
• CPC Class Codes: H04L 49/90 : Buffering arrangements
• CPC Class Codes: H04L 49/901 : using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9063 : Intermediate storage in different physical parts of a node or terminal
• CPC Class Codes: H04L 49/9078 : using an external memory or storage device
• CPC Class Codes: H04N 19/00 : Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
• CPC Class Codes: H04N 19/154 : Measured or subjectively estimated visual quality after decoding, e.g. measurement of distortion use of rate-distortion criteria H04N19/147
• CPC Class Codes: H04N 19/42 : characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/46 : Embedding additional information in the video signal during the compression process H04N19/517, H04N19/68, H04N19/70 take precedence
• CPC Class Codes: H04N 19/61 : in combination with predictive coding
• CPC Class Codes: H04N 19/70 : characterised by syntax aspects related to video coding, e.g. related to compression standards
• CPC Class Codes: H04N 19/89 : involving methods or arrangements for detection of transmission errors at the decoder
• CPC Class Codes: H04N 21/2381 : Adapting the multiplex stream to a specific network, e.g. an Internet Protocol [IP] network transmission of MPEG streams over ATM H04L12/5601
• CPC Class Codes: H04N 21/4143 : embedded in a Personal Computer [PC]
• CPC Class Codes: H04N 21/437 : Interfacing the upstream path of the transmission network, e.g. for transmitting client requests to a VOD server flow control in data networks H04L47/10; streaming protocols, e.g. RTP or RTCP, H04L65/65; scheduling or organising the servicing of application requests in data packet switching networks H04L67/60
• CPC Class Codes: H04N 21/4381 : Recovering the multiplex stream from a specific network, e.g. recovering MPEG packets from ATM cells transmission of MPEG streams over ATM H04L12/5601
• CPC Class Codes: H04N 21/4788 : communicating with other users, e.g. chatting arrangements for providing for computer conferences, e.g. chat rooms, to substation in data switching networks H04L12/1813; distributed application using peer-to-peer [P2P] networks H04L67/104
• CPC Class Codes: H04N 21/64307 : ATM
• CPC Class Codes: H04Q 11/0478 : Provisions for broadband connections
• CPC Class Codes: H04Q 2213/13034 : A/D conversion, code compression/expansion
• CPC Class Codes: H04Q 2213/13097 : Numbering, addressing
• CPC Class Codes: H04Q 2213/13141 : Hunting for free outlet, circuit or channel
• CPC Class Codes: H04Q 2213/13174 : Data transmission, file transfer
• CPC Class Codes: H04Q 2213/13204 : Protocols
• CPC Class Codes: H04Q 2213/13216 : Code signals, frame structure
• CPC Class Codes: H04Q 2213/13296 : Packet switching, X.25, frame relay
• CPC Class Codes: H04Q 2213/13322 : Integrated circuits
• CPC Class Codes: H04Q 2213/13332 : Broadband, CATV, dynamic bandwidth allocation
• CPC Class Codes: H04Q 2213/13353 : Routing table, map memory

Abstract

A remote connection digital processing device with network capability includes on a single chip asynchronous transfer mode (ATM) network protocol processing system interconnection circuits and Motion Picture Experts Group (MPEG) decoder circuits. The ATM interconnection circuits include a physical-layer medium dependent (PMD) unit connected to an ATM network. A transmission convergence (TC)/Framer unit is connected to the PMD unit. An ATM segmentation and reassembly (SAR) unit is connected to the PMD unit. Packet conversion logic is coupled to the ATM SAR unit for converting ATM packets to MPEG format. The MPEG decompression decoder circuits include a demodulator decryption unit coupled to the packet conversion logic. A video decoder is coupled to the demodulator decryption unit. An audio decoder is coupled to the demodulator decryption circuit. A display is coupled to the video decoder. Audio output devices are coupled to the audio decoder.

Claims

1. A remote connection digital processing device with network capability, comprising:

asynchronous transfer mode (ATM) network protocol processing system interconnection circuits including a physical-layer medium dependent (PMD) unit connected to an ATM network, a transmission convergence (TC)/Framer unit connected to the PMD unit, an ATM segmentation and reassembly (SAR) unit connected to the TC/Framer unit, and packet conversion logic coupled to the ATM SAR unit for converting ATM packets to a Motion Picture Experts Group (MPEG) format; and

MPEG decompression decoder circuits including a demodulator decryption unit coupled to the packet conversion logic, a video decoder coupled to the demodulator decryption unit, an audio decoder coupled to the demodulator decryption circuit, a display coupled to the video decoder, and audio output devices coupled to the audio decoder;

said ATM network protocol processing system interconnection circuits and said MPEG decompression decoder circuits being formed on a single chip.

2. A remote connection digital processing device with network capability, comprising:

network interface means for interfacing with an asynchronous transfer mode (ATM) network to receive packets of digital information in an ATM network protocol format which are representative of video and audio signals;

converter means for converting packets of digital information from the ATM network protocol format into a Motion Picture Experts Group (MPEG) format;

decoding means for decoding said packets of digital information in the MPEG format into a video signal coupled to a video output and into an audio signal coupled to an audio output;

transducer means coupled to the audio output for producing audio sounds responsive to the audio signal; and

display means coupled to the audio output for producing a video display responsive to the video signal.

3. A digital video network apparatus for receiving video data from a computer network in an ATM network protocol, comprising:

an ATM network protocol processing unit for performing segmentation of incoming ATM network protocol cells including said video data;

a central processing unit for encoding said first video data into an MPEG coded video data, wherein the encoding is performed independent of said segmentation of incoming network protocols performed by said network protocol processing unit;

a first bus coupled to said network protocol processing unit and said central processing unit for transmission of said first video data between said network protocol processing unit and said central processing unit;

an MPEG decompression unit for decompressing said MPEG coded video data to form a decoded video stream; and

a second bus coupled to said central processing unit and said MPEG decompression unit for transmitting said MPEG coded video data between said central processing unit and said MPEG decompression unit.

4. The digital video network apparatus of claim 3, wherein said network processing unit includes an ATM cell interface for receiving said ATM network protocol cells having said video data by way of a physical layer.

5. The digital video network apparatus of claim 4, wherein said network protocol unit includes a serial interface coupled to a serial PROM, a secondary port coupled to a RAM, and a DMA port coupled to said first bus.

6. The digital video network apparatus of claim 3, further including an IRAM coupled to said central processing unit by way of a third bus.

7. The digital video network apparatus of claim 6, further including a shared memory coupled to said first and second buses.

8. The digital video network apparatus of claim 3, wherein said MPEG decompression unit includes a video decoder coupled to said second bus for receiving therefrom said MPEG coded data and converting it into said decoded video stream.

9. The digital video network apparatus of claim 8, wherein said video decoder is coupled to said second bus by way of a decryption unit for decrypting said MPEG coded data if said video data is encrypted.

10. The digital video network apparatus of claim 9, further including a video coder/digital-to-analog converter for converting said decoded video stream into an analog video signal and modulating said analog video signal in either an NTSC or PAL format.

11. The digital video network apparatus of claim 10, further including a microcontroller coupled to said second bus for testing, initiating and monitoring of said video decoder.

12. A digital video network apparatus for receiving a first video data from a computer network in an ATM network protocol and transmitting a second video data to said computer network in said ATM network protocol, comprising:

an ATM network protocol processing unit for segmenting incoming ATM network protocol cells including said first video data transmitted from said computer network, and for reassembling of a second video data into an outgoing ATM network protocol cell for transmission to said computer network;

a central processing unit for encoding said first video data into an incoming MPEG coded video data and for decoding an outgoing MPEG coded video data into said second video data, wherein said central processing unit performs said encoding and decoding functions independent of said ATM network protocol processing unit performing said segmenting and re-assembling functions;

a first bus coupled to said network protocol processing unit and said central processing unit for transmission of said first and second video data between said network protocol processing unit and said central processing unit;

an MPEG decompression unit for decompressing said incoming MPEG coded video data to form a decoded video stream;

a video source for generating said outgoing MPEG coded video data; and

a second bus coupled to said central processing unit, said MPEG decompression unit, and said video source for transmitting said incoming and outgoing MPEG coded video data between said central processing unit, and said MPEG decompression unit and video source.

13. The digital video network apparatus of claim 12, wherein said network processing unit includes an ATM cell interface for receiving and transmitting by way of a physical layer said incoming and outgoing ATM network protocol cells containing said first and second video data respectively.

14. The digital video network apparatus of claim 13, wherein said network protocol unit includes a serial interface coupled to a serial PROM, a secondary port coupled to a RAM, and a DMA port coupled to said first bus.

15. The digital video network apparatus of claim 12, further including an IRAM coupled to said central processing unit by way of a third bus.

16. The digital video network apparatus of claim 15, further including a shared memory coupled to said first and second buses.

17. The digital video network apparatus of claim 12, wherein said MPEG decompression unit includes a video decoder coupled to said second bus for receiving therefrom said incoming MPEG coded data and converting it into said decoded video stream.

18. The digital video network apparatus of claim 17, wherein said video decoder is coupled to said second bus by way of a decryption unit for decrypting said MPEG coded data if said first video data is encrypted.

19. The digital video network apparatus of claim 18, further including a video coder/digital-to-analog converter for converting said decoded video stream into an analog video signal and modulating said analog video signal in either an NTSC or PAL format.

20. The digital video network apparatus of claim 19, further including a microcontroller coupled to said second bus for testing, initiating and monitoring of said video decoder.