Differential line driver

• US 5,872,811 A
• Filed: 07/08/1996
• Issued: 02/16/1999
• Est. Priority Date: 07/08/1996
• Status: Expired due to Term

• Current Assignee: Ikanos Communications Incorporated (Qualcomm, Inc.)
• Original Assignee: Analog Devices, Inc.
• Inventors: Gusinov, Alex
• Primary Examiner(s): Pham, Chi H.
• Assistant Examiner(s): Tran, Khai
• Application Number:
  US08/677,661
• Time in Patent Office: 953 Days
• Field of Search: 375/257, 375/258, 326/89, 326/90, 326/126, 326/127, 333/109, 333/116
• US Class Current: 375/257
• CPC Class Codes: H03F 2203/45352 the AAC comprising a combination of a plurality of transistors, e.g. Darlington coupled transistors
• CPC Class Codes: H03F 2203/45702 the LC comprising two resistors
• CPC Class Codes: H03F 3/45085 Long tailed pairs H03F3/45112, H03F3/45139 take precedence
• CPC Class Codes: H03K 19/00353 in bipolar transistor circuits
• CPC Class Codes: H03K 19/01812 with at least one differential stage
• CPC Class Codes: H04L 25/0274 Arrangements for ensuring balanced coupling
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end

Abstract

A differential line driver having a pair of transistors arranged as a differential pair for driving a transmission line with a differential logic output signal produced in accordance with a differential logic input signal fed to the base electrodes of the pair of transistors. The differential line driver includes circuitry for suppressing EMI emissions generated by common mode voltage switching transients produced at the collector electrodes of the pair of transistors in response to changes in the differential logic input signal. The common mode voltage switching transient suppression circuitry includes a pair of additional transistors. The differential logic input signal is fed to base electrodes of the additional transistors, and through such additional transistors, to the base electrodes of the pair of transistors of the differential pair. In one embodiment of the invention, the additional transistors are connected in a Darlington pair arrangement with the pair of transistors of the differential pair. While switching transients is the common mode voltage is still present because of the transient base current produced in the pair of transistors of the differential pair, the magnitude of the base current is attenuated by a factor β+1, where β is the beta of the additional (i.e., Darlington pair) of transistors. In another embodiment of the invention, the pair of transistors of the differential pair are NPN transistors and the additional, Darlington connected, pair of transistors are PNP transistors.

Claims

1. A data network, comprising:

(A) an unshielded transmission line;

(B) a pair of transceivers coupled together through the transmission line, each one of such transceivers comprising;

a differential line driver for feeding a differential logic output signal to the transmission line, such differential line driver comprising;

(i) a pair of transistors arranged as a differential pair for driving the transmission line with the differential logic output signal produced in accordance with an differential logic input signal fed to base electrodes of the pair of transistors; and

,

(ii) circuitry for suppressing EMI emissions generated by common mode voltage switching transients produced at collector electrodes of the pair of transistors in response to changes in the differential logic input signal.

2. A data network, comprising:

(A) an unshielded transmission line;

(B) a pair of transceivers coupled together through the transmission line, each one of such transceivers comprising;

a differential line driver for feeding a differential logic output signal to the transmission line, such differential line driver comprising;

(i) a pair of transistors arranged as a differential pair for driving the transmission line with the differential logic output signal produced in accordance with an differential logic input signal fed to base electrodes of the pair of transistors; and

,

(ii) circuitry for suppressing EMI emissions generated by common mode voltage switching transients produced at collector electrodes of the pair of transistors in response to changes in the differential logic input signal; and

wherein the EMI emission suppression circuitry includes;

a pair of additional transistors; and

wherein the differential logic input signal is fed to base electrodes of the additional transistors, and through such additional transistors, to the base electrodes of the pair of transistors of the differential pair.

3. The network recited in claim 2 wherein the additional transistors are connected in a Darlington pair arrangement with the pair of transistors of the differential pair.

4. The network recited in claim 3 wherein the pair of transistors of the differential pair are NPN transistors and the additional pair of transistors are PNP transistors.

5. The network recited in claim 4 including current sources coupled to bias the additional pair of transistors.

6. The network recited in claim 5 wherein the transmission line is a twisted pair transmission line.

7. The network recited in claim 6 wherein such network is an Asynchronous Transfer Mode (ATM) data network.

8. The network recited in claim 7 wherein the transceivers are configured to transmit and receive data at a 155 megabit (Mb) per second rate.

9. A data network wherein a pair of transceivers are coupled together through a transmission line, each one of such transceivers including a differential line driver for feeding a differential logic output signal to the transmission line, such differential line driver comprising:

a pair of transistors arranged as a differential pair for driving the transmission line with the differential logic output signal produced in accordance with an differential logic input signal fed to base electrodes of the pair of transistors;

circuitry for suppressing common mode voltage switching transients produced at collector electrodes of the pair of transistors in response to changes in the differential logic input signal.

10. A data network wherein a pair of transceivers are coupled together through a transmission line, each one of such transceivers including a differential line driver for feeding a differential logic output signal to the transmission line, such differential line driver comprising:

a pair of transistors arranged as a differential pair for driving the transmission line with the differential logic output signal produced in accordance with an differential logic input signal fed to base electrodes of the pair of transistors;

circuitry for suppressing common mode voltage switching transients produced at collector electrodes of the pair of transistors in response to changes in the differential logic input signal; and

wherein the common mode voltage switching transient suppression circuitry includes;

a pair of additional transistors; and

wherein the differential logic input signal is fed to base electrodes of the additional transistors, and through such additional transistors, to the base electrodes of the pair of transistors of the differential pair.

11. The network recited in claim 10 wherein the additional transistors are connected in a Darlington pair arrangement with the pair of transistors of the differential pair.

12. The network recited in claim 11 wherein the pair of transistors of the differential pair are NPN transistors and the additional pair of transistors are PNP transistors.

13. The network recited in claim 12 including current sources coupled to bias the additional pair of transistors.

14. A differential line driver, comprising:

a pair of transistors arranged as a differential pair for driving a transmission line with a differential logic output signal produced in accordance with a differential logic input signal fed to base electrodes of the pair of transistors;

circuitry for suppressing common mode voltage switching transients produced at collector electrodes of the pair of transistors in response to changes in the differential logic input signal.

15. A differential line driver, comprising:

a pair of transistors arranged as a differential pair for driving a transmission line with a differential logic output signal produced in accordance with a differential logic input signal fed to base electrodes of the pair of transistors;

circuitry for suppressing common mode voltage switching transients produced at collector electrodes of the pair of transistors in response to changes in the differential logic input signal; and

wherein the common mode voltage switching transient suppression circuitry includes;

a pair of additional transistors; and

wherein the differential logic input signal is fed to base electrodes of the additional transistors, and through such additional transistors, to the base electrodes of the pair of transistors of the differential pair.

16. The line driver recited in claim 15 wherein the additional transistors are connected in a Darlington pair arrangement with the pair of transistors of the differential pair.

17. The differential line driver recited in claim 16 wherein the pair of transistors of the differential pair are NPN transistors and the additional pair of transistors are PNP transistors.

18. The differential line driver recited in claim 17 including current sources coupled to bias the additional pair of transistors.

19. A differential line driver, comprising:

a first pair of bipolar transistors arranged as a differential pair;

a second pair of bipolar transistors, one of the first and second pair of transistors being NPN transistors and the other one of the pair of transistors being PNP transistors;

wherein base electrodes of the second pair of transistors are adapted for coupling to an input logic signal, emitter electrodes of the second pair of transistors being coupled to base electrodes of the first pair of transistors and collector electrodes of both transistors in the second pair of transistors being coupled to both emitters of the first pair of transistors.

20. The differential line driver recited in claim 19 including:

a first resistor coupled between the emitter of a first one of the transistors in the second pair of transistors and the base electrode of the one of the transistors in the first pair of transistors coupled thereto.