Image processing system and its method and electronic system having an image processing system

• US 5,872,872 A
• Filed: 09/29/1997
• Issued: 02/16/1999
• Est. Priority Date: 06/30/1993
• Status: Expired due to Fees

• Current Assignee: Sega Enterprises LTD.
• Original Assignee: Sega Enterprises LTD.
• Inventors: Kajiwara, Seiichi
• Primary Examiner(s): Moore, David K.
• Assistant Examiner(s): Chen, Wenpeng
• Application Number:
  US08/939,319
• Time in Patent Office: 505 Days
• Field of Search: 382/293, 382/296, 382/298, 382/276, 348/575, 348/586, 348/588, 345/114, 345/113, 345/119, 345/123, 345/126, 345/120, 345/121, 345/127, 345/139, 345/190, 345/581, 711/200, 711/202, 711/203, 711/211, 711/214, 711/217
• US Class Current: 382/296
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 17/00 Three dimensional [3D] modelling, e.g. data description of 3D objects
• CPC Class Codes: G06T 3/00 Geometric image transformations in the plane of the image
• CPC Class Codes: G06T 3/02 Affine transformations for image registration G06T3/147; for image mosaicing G06T3/4038
• CPC Class Codes: G06T 3/606 by memory addressing or mapping
• CPC Class Codes: G09G 5/14 Display of multiple viewports
• CPC Class Codes: G09G 5/346 for systems having a bit-mapped display memory
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence

Abstract

An image processing system which allows a variety of different types of split-screen image data, including window displays, to be generated. The image processing system of the present invention further can display windows of various shapes to ensure diversified use of display screens. The image processing system also enables various types of movement and rotation transformation as well as scaling transformation to be performed while reducing the calculation load on the CPU.

Claims

1. An image processing system for use in an electronic system including an image memory for storing image information and a CPU, said image processing system comprising:

a plurality of signal processing means functionally connected with said CPU to be supplied with various parameters for coordinate transformation processing, each of said plurality of signal processing means having means for executing coordinate transformation processing based on the parameters in connection with a background image to be displayed on a monitor screen;

switching means, connected to said plurality of signal processing means, for selecting one of said plurality of signal processing means to output a signal including a transformed coordinate data for each pixel of the background image to be displayed, said switching means selecting one of said plurality of signal processing means according to a switching signal preset for each pixel by said CPU; and

an address generation means, connected to the output of said switching means, for generating an address for each pixel of image information based on said signal, including the transformed coordinate data and, connected to said image memory, for accessing image information in said image memory with the generated address data;

wherein said address data is generated only for each pixel of image information to be displayed;

thereby providing, in a sequence of said selection by said switching means, a set of address data for generating a combined background image.

2. An image processing system as claimed in claim 1, wherein said signal processing means each comprising:

a parameter register for storing parameters used for performing movement transformation processing and/or rotation transformation processing;

a matrix operation circuit for performing movement transformation processing and/or rotation transformation processing using said parameters;

a coefficient RAM for storing data as coefficients; and

a coefficient RAM access circuit for accessing said coefficient RAM and for calling said coefficients.

3. An image processing system as claimed in claim 2, wherein said display switching signal is sent from one of said coefficient RAMs to said switching means.

4. An image processing system as claimed in claim 2, wherein said address generation means comprising:

an AND/OR operation circuit connected to said switching means; and

an image memory access circuit connected to said AND/OR operation circuit.

5. An image processing method to be performed on an image processing system as defined in claim 1, comprising the steps of:

supplying coordinate parameters before coordinate transformation to each of said plurality of signal processing means;

executing coordinate transformation processing based on said coordinate parameters in each of said plurality of said signal processing means;

selectively switching outputs of said plurality of said signal processing means according to a switching signal supplied from said CPU for each pixel to supply the address generation means with a signal, including the transformed coordinate data from the selected one of said outputs of said plurality of said signal processing means;

generating an address for each pixel of a background image based on the signal, including the transformed coordinate data thereby providing, in sequence of said selective switching, a set of address data; and

generating a combined background image data by accessing the image memory with the address data for displaying a plurality of images separately generated on split areas of a monitor screen, wherein only the background image data to be displayed is generated.

6. An electronic system comprising:

(1)a CPU;

(2) a video RAM;

(3) a video processor connected to said video RAM and said CPU, comprising the following (a) to (c);

(a) a plurality of signal processing means functionally connected with said CPU to be supplied with various parameters for coordinate transformation processing, each of said plurality of signal processing means having means for executing coordinate transformation processing based on the parameters in connection with a background image to be displayed on a monitor screen;

(b) switching means, connected to said plurality of signal processing means, for selecting one of said plurality of signal processing means to output a signal, including a transformed coordinate data for each pixel of the background image to be displayed, said switching means selecting one of said plurality of signal processing means according to a switching signal preset for each pixel by said CPU; and

(c) an address generation means, connected to the output of said switching means, for generating an address for each pixel of image information based on said signal, including the transformed coordinate data and connected to said image memory, for accessing image information in said image memory with the generated address data;

wherein said address data is generated only for each pixel of image information to be displayed;

thereby providing, in a sequence of said selection by said switching means, a set of address data for generating a combined background image.

9. An electronic system as claimed in claim 6, further comprising a display device for displaying an image according to image data generated from image information.

7. An electronic system comprising:

(1) a CPU;

(2) a first video processor;

(3) a first video RAM, connected to said first video processor, for storing image information;

(4) a second video processor, including a background image generation section and a display control section connected to said background image generation section; and

(5) a second video RAM, connected to said second video processor, for storing image information,

wherein said background image generation section includes the following (a) to (c);

(a) a plurality of signal processing means functionally connected with said CPU to be supplied with various parameters for coordinate transformation processing, each of said plurality of signal processing means having means for executing coordinate transformation processing based on the parameters in connection with a background image to be displayed on a monitor screen;

(b) switching means, connected to said plurality of signal processing means, for selecting one of said plurality of signal processing means to output a signal, including a transformed coordinate data for each pixel of the background image to be displayed, said switching means selecting one of said plurality of signal processing means according to a switching signal preset for each pixel by said CPU; and

(c) an address generation means, connected to the output of said switching means, for generating an address for each pixel of image information based on said signal, including the transformed coordinate data and, connected to said second image memory, for accessing image information in said second image memory with the generated address data;

wherein said address data is generated only for each pixel of image information to be displayed

thereby providing, in a sequence of said selection by said switching means, a set of address data for generating a combined background image.

8. An electronic system comprising:

(1)a CPU;

(2) a bus line connected to said CPU;

(3) a bus controller for controlling the flow of signals on said bus line;

(4) a first image information processing section, including the following

     1) to

     3);

1) a first video processor, connected to said bus line, for controlling the generation of sprite image data;

2) a first video RAM, connected to said first video processor, for storing image information for generating video sprite image data; and

3) a frame buffer for expanding said sprite image data;

(5) a second image information processing section, including the following

     1) and

     2);

1) a second video processor connected to said bus line including;

a background image processing section for generating background image data; and

a display control section, connected to said background image generation section and to said first image processing section, for controlling said image data in order to combine said sprite image data and said background image data; and

2) a second video RAM, connected to said second video processor, for storing image information for processing background image data, wherein said background image generation section includes the following (a) to (c);

(a) a pair of signal processing means, functionally connected to said CPU via said bus line to be supplied with various parameters, for coordinate transformation processing, each of said plurality of signal processing means for performing coordinate transformation processing based on the parameters in connection with a background image to be displayed on a monitor screen;

(b) switching means, connected to said pair of signal processing means, for selecting one of said plurality of signal processing means to output a signal, including a transformed coordinate data for each pixel of the background image to be displayed, said switching means selecting one of said pair of signal processing means according to a switching signal preset for each pixel by said CPU; and

(c) an address generation means, connected to the output of said switching means, for generating an address for each pixel of image information based on said signal, including the transformed coordinate data and, connected to said second video RAM, for accessing image information in said second video RAM with the generated address data;

wherein said address data is generated only for each pixel of image information to be displayed

thereby providing, in a sequence of said selection by said switching means, a set of address data for generating a combined background image, including images processed separately by said pair of signal processing means.