Method and apparatus for parallel high speed data transfer

• US 5,872,959 A
• Filed: 09/10/1996
• Issued: 02/16/1999
• Est. Priority Date: 09/10/1996
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Nguyen, Trung T., Yang, Henry, Bach, Randy E., Daberkow, Kevin
• Primary Examiner(s): Butler, Dennis M.
• Application Number:
  US08/711,502
• Time in Patent Office: 889 Days
• Field of Search: 395/551, 395/552, 395/558, 395/559, 395/845, 395/309
• US Class Current: 713/401
• CPC Class Codes: G06F 13/4217 with synchronous protocol
• CPC Class Codes: H04L 7/0041 Delay of data signal
• CPC Class Codes: H04L 7/005 Correction by an elastic buffer
• CPC Class Codes: H04L 7/02 Speed or phase control by the received code signals, the signals containing no special synchronisation information H04L7/0075 takes precedence
• CPC Class Codes: H04L 7/046 using a dotting sequence
• CPC Class Codes: H04L 7/10 Arrangements for initial synchronisation

Abstract

The present invention concerns a method for eliminating or reducing clock skew introduced by differing signal propagation delays across a data bus. At high bus clock frequencies the time delay differences caused by path length differences can be catastrophic and must be eliminated by expensive layout techniques. An input/output (I/O) architecture is proposed here which tailors a delay to each individual data line, and thereby aligns all the incoming data. Furthermore, a clock signal is provided to indicate the optimal data sampling time. In the described embodiment, this circuit enables the transmission of four 32 bit words in parallel in one clock cycle of a 250 MHz processor.

Claims

1. A data bus interface for fast parallel I/O comprising:

a core interface configured to accept output data from a core for transmission and configured to provide to said core input data which has been received;

a data transmission unit coupled to said core interface to receive said output data for transmission and configured to drive a plurality of output signals representing said output data across a data bus in a fixed-phase relationship with a bus clock signal; and

a data reception unit coupled to said data bus to receive a plurality of input signals representing said input data and configured to synchronize said plurality of input signals to each other in a fixed-phase relationship with said bus clock signal, thereby reducing clock skew of said plurality of input signals, said data reception unit comprising;

a plurality of delay elements each coupled to receive a corresponding one of said plurality of input signals;

a first-in first-out buffer for synchronizing said input data to a core clock signal;

a data delay adjust unit coupled to an output of said first-in first-out buffer and configured to set the individual delays of said plurality of delay elements;

a demultiplexer coupled to receive a delayed input data signal from each of said plurality of delay elements, coupled to receive a bus clock signal, and configured to time-demultiplex the delayed input data signal from each of said plurality of delay elements in response to changes in said bus clock signal; and

a plurality of data latches coupled to receive time-demultiplexed output data from said demultiplexer, and thereafter synchronously provide said time-demultiplexed output data as an input signal to said first-in first-out buffer.

2. The data bus interface for fast parallel I/O as recited in claim 1, wherein each of said plurality of delay elements comprises a differential amplifier with a variable current source which is configured to permit adjustment of signal propagation time through the differential amplifier.

3. The data bus interface for fast parallel I/O as recited in claim 1, wherein said data transmission unit comprises:

a four-phase clock generator coupled to receive a second core clock signal and configured to provide delayed versions of said second core clock signal to form a four-phase clock signal; and

an array of line drivers, each of which comprises;

a four-bit buffer configured to store data for transmission; and

a first multiplexer coupled to receive said four-phase clock signal, coupled to receive data from said four-bit buffer, and configured to multiplex data from said four-bit buffer in response to changes in said four-phase clock signal.

4. The data bus interface for fast parallel I/O as recited in claim 3, wherein each of said array of line drivers further comprises:

a second multiplexer coupled to receive an output signal from said first multiplexer, coupled to receive a test signal, and configured to pass one of said output or test signals in response to a testing mode signal; and

a buffer coupled to drive the output signal from said second multiplexer onto a bus data line.

5. The data bus interface for fast parallel I/O as recited in claim 3, wherein said plurality of data latches includes a set of four data latches.

6. The data bus interface for fast parallel I/O as recited in claim 5, wherein said time-demultiplexed output data includes four bits of time-demultiplexed output data.

7. A computer system which comprises:

a data bus which is coupled between elements configured to transmit and receive data across said data bus, each of said elements comprising;

a core; and

a data bus interface coupled to said core, said data bus interface including;

a core interface configured to accept output data from said core for transmission and configured to provide to said core input data which has been received;

a data transmission unit coupled to said core interface to receive said output data for transmission and configured to drive a plurality of output signals representing said output data across said data bus in a fixed-phase relationship with a bus clock signal; and

a data reception unit coupled to said data bus to receive a plurality of input signals representing said input data and configured to synchronize said plurality of input signals to each other in a fixed-phase relationship with said bus clock signal, thereby reducing clock skew of said plurality of input signals, said data reception unit including;

a plurality of delay elements each coupled to receive a corresponding one of said plurality of input signals;

a first-in first-out buffer for synchronizing said input data to a core clock signal;

a data delay adjust unit coupled to an output of said first-in first-out buffer and configured to set the individual delays of said plurality of delay elements;

a demultiplexer coupled to receive a delayed input data signal from each of said plurality of delay elements, coupled to receive a bus clock signal, and configured to time-demultiplex the delayed input data signal from each of said plurality delay elements in response to changes in said bus clock signal; and

a plurality of data latches coupled to receive time-demultiplexed output data from said demultiplexer, and thereafter synchronously provide said time-demultiplexed output data as an input signal to said first-in first-out buffer.

8. The computer system as recited in claim 7, wherein each of said plurality of delay elements comprises a differential amplifier with a variable current source which is configured to permit adjustment of signal propagation time through the differential amplifier.

9. The computer system as recited in claim 7, wherein said data transmission unit comprises:

a four-phase clock generator coupled to receive a second core clock signal and configured to provide delayed versions of said second core clock signal to form a four-phase clock signal; and

an array of line drivers, each of which comprises;

a four-bit buffer configured to store data for transmission; and

a first multiplexer coupled to receive said four-phase clock signal, coupled to receive data from said four-bit buffer, and configured to multiplex data from said four-bit buffer in response to changes in said four-phase clock signal.

10. The computer system as recited in claim 9, wherein each of said array of line drivers further comprises:

a second multiplexer coupled to receive an output signal from said first multiplexer, coupled to receive a test signal, and configured to pass one of said output or test signals in response to a testing mode signal; and

a buffer coupled to drive the output signal from said second multiplexer onto a bus data line.

11. The computer system as recited in claim 9, wherein said plurality of data latches includes a set of four data latches.

12. The computer system as recited in claim 11, wherein said time-demultiplexed output data includes four bits of time-demultiplexed output data.