Resumption of preempted non-privileged threads with no kernel intervention

• US 5,872,963 A
• Filed: 02/18/1997
• Issued: 02/16/1999
• Est. Priority Date: 02/18/1997
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: Silicon Graphics Incorporated (Graphics Properties Holdings, Inc.)
• Inventors: Bitar, Nawaf K., English, Robert M., Ananthanarayanan, Rajagopal, Petruncola, Alexander D., Craig, David
• Primary Examiner(s): Pan, Daniel H.
• Application Number:
  US08/800,968
• Time in Patent Office: 728 Days
• Field of Search: 395/741, 395/800.3, 395/740, 395/200.45, 395/712, 395/670, 395/580, 395/704, 395/678, 395/183.14, 395/185.05, 395/733, 364/757, 364/DIG. 1, 364/DIG. 2, 711/111, 711/118, 711/113
• US Class Current: 712/233
• CPC Class Codes: G06F 9/461 Saving or restoring of program or task context
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system

Abstract

A system and method for context switching between a first and a second execution entity (such as a thread) without having to enter into protected kernel mode. The system includes a memory and a plurality of processors, wherein each of the plurality of processors operates within both a user mode and a protected kernel mode and includes a program counter and a plurality N of registers. The first and second execution entities have user states defined by a program counter value, a context identifier value and N register values. To switch context, an execution entity such as a thread, while in user mode, writes the user state of the first execution entity to memory. It then restores the user state of the second execution entity by writing register values associated with the second execution entity to all but a first register and writing the context identifier value to a context identifier location. The program counter value is then written to the first register and a jump performed to the program counter value stored in the first register while the last remaining register value is loaded to the first register. Each of these steps is performed in user mode; the result is an efficient way of switching from one user thread to the next user thread without entry into kernel space.

Claims

1. In a computer system having a processor and a memory, wherein the processor operates within both a user mode and a protected kernel mode and includes a program counter and a plurality N of registers, wherein the N registers include a first register, a method of remaining in user mode while switching between a first execution entity and a second execution entity, wherein the second execution entity has a user state defined by a program counter value, a context identifier value and N register values, the method comprising the steps of:

providing an instruction set capable of executing a register load instruction during execution of a jump instruction;

while remaining in user mode, writing the user state of the first execution entity to memory; and

while remaining in user mode, restoring the user state of the second execution entity, wherein the step of restoring the user state of the second execution entity includes the steps of;

writing register values associated with the second execution entity to all but the first register;

writing the context identifier value to a context identifier location;

writing the program counter value to the first register; and

jumping to the program counter value stored in the first register, wherein the step of jumping includes loading a last remaining register value associated with the second execution entity to the first register while jumping to said program counter value.

2. The method according to claim 1, wherein the step of writing the user state of the first execution entity to memory includes storing a program counter value associated with the first execution entity to memory.

3. The method according to claim 1, wherein the step of writing the user state of the first execution entity to memory includes marking the first execution entity so that it cannot be restarted until the switch from the first execution entity to the second execution entity has completed.

4. The method according to claim 3, wherein the step of marking the first execution entity includes the steps of:

providing a preempt bit vector; and

marking a bit in the preempt bit vector associated with the first execution entity; and

wherein the step of writing the user state of the first execution entity to memory includes the steps of;

locating a register save area associated with the first execution entity;

storing a program counter value and a context identifier value to the register save area associated with the first execution entity;

storing register values read from the N registers to the register save area associated with the first execution entity; and

after each of the above steps has executed, setting the bit in the preempt bit vector associated with the first execution entity to a value indicating that the first execution entity can now be executed.

5. The method according to claim 4 wherein the step of providing a preempt bit vector includes the step of allocating a register save area and a predefined thread to each bit in the preempt bit vector.

6. The method according to claim 4 wherein the step of writing the user state of the first execution entity to memory includes allocating an available register save area to store the user state of the first execution entity.

7. The method according to claim 4 wherein the step of restoring the user state of the second execution entity further includes locating a register save area associated with the second execution entity;

wherein the step of writing the context identifier value to a context identifier location includes reading the context identifier value from one of the N registers; and

wherein the step of writing register values associated with the second execution entity includes;

reading the context identifier value from the register save area associated with the second execution entity;

writing the context identifier value to one of the N registers;

reading N-1 register values from the register save area associated with the second execution entity; and

writing the N-I register values to N-1 of the N registers.

8. The method according to claim 1 wherein the step of restoring the user state of the second execution entity further includes determining a register save area associated with the second execution entity;

wherein the step of writing the context identifier value to a context identifier location includes reading the context identifier value from one of the N registers; and

wherein the step of writing register values associated with the second execution entity includes;

reading the context identifier value from the register save area associated with the second execution entity;

writing the context identifier value to one of the N registers;

reading N-1 register values from the register save area associated with the second execution entity; and

writing the N-1 register values to N-1 of the N registers.

9. In a computer system having a processor and a memory, wherein the processor operates within both a user mode and a protected kernel mode and includes a program counter and a plurality N of registers, wherein the N registers include a first register a method of remaining in user mode while switching between a first execution entity and a second execution entity, wherein the second execution entity has a user state defined by a program counter value, a context identifier value and N register values, the method comprising the steps of:

providing an instruction set capable of executing a register load instruction during execution of a jump instruction, wherein the instruction set includes a jump instruction having a delay slot;

writing the user state of the first execution entity to memory; and

restoring the user state of the second execution entity, wherein the step of restoring the user state of the second execution entity includes the steps of;

writing register values associated with the second execution entity to all but the first register;

writing the context identifier value to a context identifier location;

writing the program counter value to the first register; and

jumping to the program counter value stored in the first register, wherein the step of jumping includes loading a last remaining register value to the first register while jumping to said program counter value.

10. The method according to claim 9, wherein the step of writing the user state of the first execution entity to memory includes storing a program counter value associated with the first execution entity to memory.

11. The method according to claim 9, wherein the step of writing the user state of the first execution entity to memory includes marking the first execution entity so that it cannot be restarted until the switch from the first execution entity to the second execution entity has completed.

12. The method according to claim 11, wherein the step of marking the first execution entity includes the steps of:

providing a preempt bit vector; and

marking a bit in the preempt bit vector associated with the first execution entity; and

wherein the step of writing the user state of the first execution entity to memory includes the steps of;

locating a register save area associated with the first execution entity;

storing a program counter value and a context identifier value to the register save area associated with the first execution entity;

storing register values read from the N registers to the register save area associated with the first execution entity; and

after each of the above steps has executed, setting the bit in the preempt bit vector associated with the first execution entity to a value indicating that the first execution entity can now be executed.

22. The computer system according to claim 11, wherein the instruction set includes a very long instruction word (VLIW) architecture capable of placing a load register instruction within the same VLIW instruction as the jump instruction.

13. In a computer system having a processor and a memory, wherein the processor operates within both a user mode and a protected kernel mode and includes a program counter and a plurality N of registers, wherein the N registers include a first register, a method of remaining in user mode while switching between a first execution entity and a second execution entity, wherein the second execution entity has a user state defined by a program counter value, a context identifier value and N register values, the method comprising the steps of:

providing an instruction set capable of executing a register load instruction during execution of a jump instruction, wherein the instruction set includes a very long instruction word (VLIW) architecture capable of placing a load register instruction within the same VLIW instruction as the jump instruction;

writing the user state of the first execution entity to memory; and

restoring the user state of the second execution entity, wherein the step of restoring the user state of the second execution entity includes the steps of;

writing register values associated with the second execution entity to all but the first register;

writing the context identifier value to a context identifier location;

writing the program counter value to the first register; and

jumping to the program counter value stored in the first register, wherein the step of jumping includes loading a last remaining register value to the first register while jumping to said program counter value.

14. The method according to claim 13, wherein the step of writing the user state of the first execution entity to memory includes storing a program counter value associated with the first execution entity to memory.

15. The method according to claim 13, wherein the step of writing the user state of the first execution entity to memory includes marking the first execution entity so that it cannot be restarted until the switch from the first execution entity to the second execution entity has completed.

16. The method according to claim 15, wherein the step of marking the first execution entity includes the steps of:

providing a preempt bit vector; and

marking a bit in the preempt bit vector associated with the first execution entity; and

wherein the step of writing the user state of the first execution entity to memory includes the steps of;

locating a register save area associated with the first execution entity;

storing a program counter value and a context identifier value to the register save area associated with the first execution entity;

storing register values read from the N registers to the register save area associated with the first execution entity; and

after each of the above steps has executed, setting the bit in the preempt bit vector associated with the first execution entity to a value indicating that the first execution entity can now be executed.

17. A computer system, comprising:

memory;

a processor connected to the memory, wherein the processor operates within both a user mode and a protected kernel mode and includes an instruction set capable of executing a register load instruction during execution of a jump instruction and a memory structure having a program counter and a plurality N of registers, wherein the N registers include a first register; and

program code for switching between a first execution entity and a second execution entity while remaining in user mode, wherein the second execution entity has a user state defined by a program counter value, a context identifier value and N register values, wherein the program code includes;

program code for writing the user state of the first execution entity to memory;

program code for restoring the user state of the second execution entity, including program code for writing register values associated with the second execution entity to all but the first register, for writing the context identifier value to a context identifier location and for writing the program counter value to the first register, and

program code for jumping to the program counter value stored in the first register, including program code for loading the last remaining register value to the first register while jumping to said program counter value.

18. The computer system according to claim 17, wherein the memory includes:

a preempt bit vector which indicates when an execution entity has been preempted;

a first register save area used to store user state associated with the first execution entity; and

a second register save area used to store user state associated with the second execution entity.

19. The computer system according to claim 17, wherein the memory includes:

a preempt bit vector which indicates when an execution entity has been preempted; and

a plurality of register save areas used to store user state associated with preempted execution entities; and

wherein the program code for writing the user state of the first execution entity to memory includes program code for allocating a register save area and a predefined thread to each bit in the preempt bit vector.

20. The computer system according to claim 17, wherein the memory includes:

a preempt bit vector which indicates when an execution entity has been preempted; and

a plurality oft register save areas used to store user state associated with preempted execution entities; and

wherein the program code for writing the user state of the first execution entity to memory includes program code for allocating an available register save area to store the user state of the first execution entity.

21. The computer system according to claim 17, wherein the instruction set includes a jump instruction having a delay slot.