Massively parallel computer including auxiliary vector processor

• US 5,872,987 A
• Filed: 09/16/1996
• Issued: 02/16/1999
• Est. Priority Date: 08/07/1992
• Status: Expired due to Fees

• Current Assignee: Thinking Machines Corporation (Oracle Corporation)
• Original Assignee: Thinking Machines Corporation (Oracle Corporation)
• Inventors: Hillis, W. Daniel, Smith, Scott J., Douglas, David C., Ganmukhi, Mahesh N., Wade, Jon P., Hill, Jeffrey V., Abuhamdeh, Zahi S., Cassiday, Daniel R., Zak, Robert C. Jr., Wong-Chan, Monica C., Steele, Guy Lewis Jr., St. Pierre, Margaret A., Yang, Shaw-Wen, Lordi, Robert D.
• Primary Examiner(s): Bowler, Alyssa H.
• Assistant Examiner(s): Nguyen, Dzung C.
• Application Number:
  US08/714,635
• Time in Patent Office: 883 Days
• Field of Search: 395/800, 395/800.01, 395/800.1, 395/800.11, 395/800.16, 364/DIG. 1
• US Class Current: 712/3
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus
• CPC Class Codes: G06F 15/8084 Special arrangements thereof, e.g. mask or switch
• CPC Class Codes: G06F 15/8092 Array of vector units
• CPC Class Codes: G06F 21/52 during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow

Abstract

A massively-parallel computer includes a plurality of processing nodes and at least one control node interconnected by a network. The network faciliates the transfer of data among the processing nodes and of commands from the control node to the processing nodes. Each each processing node includes an interface for transmitting data over, and receiving data and commands from, the network, at least one memory module for storing data, a node processor and an auxiliary processor. The node processor receives commands received by the interface and processes data in response thereto, in the process generating memory access requests for facilitating the retrieval of data from or storage of data in the memory module. The node processor further controlling the transfer of data over the network by the interface. The auxiliary processor is connected to the memory module and the node processor. In response to memory access requests from the node processor, the auxiliary processor performs a memory access operation to store data received from the node processor in the memory module, or to retrieve data from the memory module for transfer to the node processor. In response to auxiliary processing instructions from the node processor, the auxiliary processor performs data processing operations in connection with data in the memory module.

Claims

1. A massively-parallel computer comprising a plurality of processing nodes and at least one control node interconnected by a network for facilitating the transfer of data among the processing nodes and of commands from the control node to the processing nodes, each processing node comprising:

A. an interface for transmitting data over, and receiving data and commands from, said network;

B. at least one memory module for storing data in a plurality of storage locations each identified by an address;

C. a node processor for receiving commands received by the interface and for processing data in response thereto, said node processor generating (i) auxiliary processing instructions, (ii) memory access requests for facilitating the retrieval of data from or storage of data in said memory module, and (iii) said node processor further controlling the transfer of data over said network by said interface; and

D. an auxiliary processor connected to said memory module, said auxiliary processor including;

(i) a memory interface for performing memory access operations in response to said memory access requests from said node processor, to store data received from said memory module for transfer to said node processor,

(ii) a data processor for performing data processing operations in response to said auxiliary processing instructions from said node processor, said data processor including a data processing circuit and a resister file that includes a plurality of registers each identified by a resister identification, said data processor, also in response to data processing control signals, performing data processing elemental operations and generating processed data items which correspond to input data items that represent the contents of selected registers and storing the processed data items in selected registers, the input data items that are provided for each elemental operation and the processed data items that are produced for each elemental operation representing vector elements of corresponding vectors; and

(iii) a control interface for receiving (a) said auxiliary processing instructions from said node processor and for generating data processing control signals in response thereto, and (b) said memory access requests from said node processor and for generating memory access control signals in response thereto,

(iv) said control interface further selectively generating memory access control signals in response to receipt of auxiliary processing instructions, an address, a data processing identifier that identifies one of a plurality of data processing operations, and a load/store identifier that includes a register identifier, said control interface in response to a load/store identifier that identifies a load operation enabling said memory module to selectively retrieve data from a storage location in said memory module identified by the received address for transfer to the identified resister in said data processor, and in response to a load/store identifier that identifies a store operation enabling said memory module to store in a storage location identified by the received address data received from said identified register in said data processor,

(v) said control interface further including a conditionalizing circuit for selectively disabling execution by said data processor of selected elemental operations by disabling storage of processed data items generated by said data processing circuit for said selected elemental operations, said conditionalizing circuit including;

a. a vector mask register including a plurality of vector mask bits, each vector mask bit being associated with an elemental operation, and each bit having a selected condition;

b. a mask bit selection circuit for selecting a vector mask register for an elemental operation; and

c. a storage control circuit for controlling storage of processed data items by said register file for an elemental operation in response to the condition of the selected vector mask bit.

2. A computer as defined in claim 1 in which said conditionalizing circuit includes:

A. a vector mask register including a plurality of vector mask bits, each vector mask bit being associated with an elemental operation, and each bit having a selected condition;

B. a mask bit selection circuit for selecting a vector mask bit of said vector mask register for an elemental operation; and

C. a storage control circuit for controlling storage of processed data items by said register file for an elemental operation in response to the condition of the selected vector mask bit.

3. A computer as defined in claim 1 in which said conditionalizing circuit further includes a processor mode flag having a selected condition, the storage control circuit further operating in response to the condition of said processor mode flag, in response to the processor mode flag having one selected condition the storage control circuit controlling storage of processed data by said register file in response to the condition of the selected vector mask bit, and in response to the processor mode flag having a second selected condition the storage control circuit enabling storage of processed data items by said register file.

4. A computer as defined in claim 3 in which, in response to a load/store instruction, said control circuit generates memory access control signals to enable, for each of a plurality of successive elemental operations, said memory interface to perform a memory access operation and said register file to perform a register access operation to selectively facilitate the transfer of data between a selected storage location of said memory module and a selected register of said register file.

5. A computer as defined in claim 4 in which said conditionalizing circuit further selectively disables transfer of data by said register file and memory interface for selected elemental operations in response to the conditions of the vector mask bits, said conditionalizing circuit including a load/store mode flag having selected conditions for selectively controlling use of said vector mask bits to disable such transfers.

6. A computer as defined in claim 1 in which operations for each elemental operation in response to an auxiliary processing instruction proceed through a sequence of processing stages, said control interface in each stage generating processing stage control signals for enabling said register file and said data processing circuit to perform predetermined operations in said stage, said control interface including:

A. a token generator for, in response to receipt of an auxiliary processing instruction, generating a series of data processing enabling tokens corresponding to the number of elemental operation to be performed;

B. a data processing token shift register comprising a series of data processing token shift register stages corresponding to the number of processing stages, said token shift register iteratively receiving data processing enabling tokens from said token generator and shifting them through said data processing token shift register stages; and

C. a series of processing stage control signal generators (46), each associated with one of said data processing stage control signals for enabling said register file and said data processing circuit to perform predetermined operations for the associated stage.

7. A computer as defined in claim 6 further comprising:

A. an initial token spacing control signal generating circuit (202,

     203) for generating a spacing control signal at the expiration of a selected time period following the generation by the token generator of the first of a series of data processing enabling tokens for an auxiliary processing instruction;

B. a scheduler circuit (200) for controlling the initiation by the token generator of generating of data processing enabling tokens in response to receipt by the auxiliary processor of an auxiliary processing instruction and the generation by the initial token spacing control circuit of the spacing control signal so that data processing enabling tokens for an auxiliary processing instruction will have a selected spacing relationship in said processing stages with respect to a preceding auxiliary processing instruction.