System and method for encoding data to reduce power and time required to write the encoded data to a flash memory

• US 5,873,112 A
• Filed: 10/15/1996
• Issued: 02/16/1999
• Est. Priority Date: 02/23/1996
• Status: Expired due to Term

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Micron Technology, Inc.
• Inventors: Norman, Robert D.
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): Langjahr, David
• Application Number:
  US08/730,181
• Time in Patent Office: 854 Days
• Field of Search: 365/185.11, 365/201, 365/230.03, 371/40.11, 711/103
• US Class Current: 711/103
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method and system in which X-bit packets of bits (where X is an integer) are encoded to generate X-bit packets of encoded bits for writing to erased cells of a flash memory array, where less power is consumed to write a bit having a first value to an erased cell than to write a bit having a second value to the cell. Preferably, a count signal is generated for each packet of raw bits indicating the number of bits of the packet having the first (or second) value, the count signal is processed to generate a control signal which determines an encoding for the packet, and the raw bits of the packet are encoded according to a scheme determined by the control signal. In some embodiments, each erased cell is indicative of the binary value "1", the count signal is compared to a reference value (indicative of X/2) to generate a control signal determining whether the packet should undergo polarity inversion, and the packet is inverted (or not inverted) depending on the value of the control signal. In alternative embodiments, a count signal is generated for each packet of bits to be written to erased cells of an array (where the count signal indicates the number of bits in the packet having a particular value), and each packet is encoded in a manner determined by the corresponding count signal to reduce the power needed to write the encoded bits to the erased cells. Preferably, flag bits indicative of the encoding of each packet are generated, and the flag bits (as well as the encoded packets) are stored in cells of the flash memory array.

Claims

1. A method for encoding binary bits for writing to a non-volatile memory device, said method comprising the steps of:

selecting a plurality of packets of the bits, each of the packets comprising X binary bits;

determining the number of bits of said X binary bits in each of the packets which have a first value and the number of bits of said X binary bits in said each of the packets which have a second value, by accumulating data indicative of the number of bits in each of a number of subsets of said each of the packets which have the first value; and

for each of the packets, encoding said X binary bits to a first set of values when the number of bits of said first value exceeds the number of bits of said second value, and encoding said X binary bits to a second set of values when the number of bits of said second value exceeds the number of bits of said first value.

2. A method of programming a non-volatile memory device, comprising the steps of:

providing a plurality of packets of bits, each of said packets comprising X number of binary bits;

for each of the packets, determining the number of binary bits representative of a first value and the number of binary bits representative of a second value, by accumulating data indicative of the number of binary bits in each of a number of subsets of said each of the packets which are representative of the first value; and

for each of the packets, selecting an encoding state from at least two possible encoding states, said encoding state selected to require less power for programming, said encoding state selected in reference to the determined number of binary bits in said each of the packets which are representative of the first value and the second value; and

programming at least a portion of said non-volatile memory device in accordance with said selected encoding state for said each of the packets.

3. A method for encoding binary bits to be written to erased cells of an array of flash memory cells, said method including the steps of:

(a) processing X-bit packets of the bits to generate count signals, wherein a count signal is generated for each of the packets by accumulating data indicative of the number of bits which have a first value in each of a number of subsets of said each of the packets, each said count signal is indicative of how many bits of the corresponding one of the packets have the first value, and X is an integer; and

(b) encoding the packets to generate X-bit encoded packets of encoded binary bits, by performing a first encoding operation on each of the packets whose count signal satisfies a first criterion and a second encoding operation on each of the packets whose count signal satisfies a second criterion but does not satisfy the first criterion, so that each of the encoded packets consists of P encoded bits having the first value and Q encoded bits having a second value, where P and Q are integers satisfying X=P+Q, and P is not less than Q.

4. The method of claim 3, also including the step of:

(c) writing the encoded packets to a first subset of the erased cells of the array.

5. The method of claim 4, wherein less power is consumed during step (c) to write a binary bit having the first value to each of the erased cells than to write a binary bit having the second value to said each of the erased cells.

6. The method of claim 4, also including the steps of:

(d) generating polarity flag bits for the encoded packets, wherein the polarity flag bits includes a set of at least one polarity flag bit for each of the encoded packets, and each said set is indicative of which of the first encoding operation and the second encoding operation was performed to generate said each of the encoded packets; and

(e) writing the polarity flag bits to a second subset of the erased cells of the array.

7. The method of claim 6, wherein step (e) includes the steps of:

collecting the polarity flag bits in a shift register, where the shift register contains a bit for each of the encoded packets; and

writing the polarity flag bits from the shift register to said second subset of the erased cells of the array.

8. The method of claim 6, also including the steps of:

(f) reading the polarity flag bits and the encoded packets from the array;

(g) temporarily storing the polarity flag bits; and

(h) performing an inverse of the first encoding operation on each of the encoded packets read during step (f) for which one of the polarity flag bits stored during step (g) indicates that the first encoding operation was performed to generate said each of the encoded packets read during step (f).

9. A method for encoding binary bits to be written to erased cells of an array of flash memory cells, said method including the steps of:

(a) storing a number of X-bit packets of the bits in a buffer memory, where X is an integer;

(b) reading each of the packets from the buffer memory and generating a packet count signal from data indicative of the number of bits which have a first one of a first value and a second value in each of at least two subsets of said each of the packets, said packet count signal being indicative of how many bits of said each of the packets have said first one of the first value and the second value;

(c) comparing each said packet count signal to a reference value, to determine each of the packets whose packet count signal is greater than the reference value and to determine each of the packets whose packet count signal is not greater than the reference value;

(d) performing a first encoding operation on each of the packets whose packet count signal is greater than the reference value to generate an X-bit encoded packet of encoded binary bits for said each of the packets; and

(e) performing a second encoding operation on each of the packets whose packet count signal is not greater than the reference value to generate an X-bit encoded packet of encoded binary bits for said each of the packets, whereby steps (d) and (e) together accomplish generation of a set of encoded packets.

10. The method of claim 9, wherein step (b) includes the steps of:

reading a sequence of the subsets of said each of the packets from the buffer memory and generating count signals therefrom, said count signals including a count signal for each of the subsets indicative of how many bits of said each of the subsets have said first one of said first value and a second value;

adding the count signals for said each of the packets to generate said packet count signal for said each of the packets.

11. The method of claim 9, wherein each of the packets whose packet count signal is not greater than the reference value consists of more bits having a second value than bits having the first value, and wherein each of the encoded packets generated during step (e) consists of more bits having the first value than bits having the second value.

12. The method of claim 9, wherein the second encoding operation consists of inverting each of the bits of said each of the packets whose packet count signal is not greater than the reference value.

13. The method of claim 9, also including the step of:

(f) writing the encoded packets to a first subset of the erased cells of the array.

14. The method of claim 13, wherein less power is consumed during step (f) to write a binary bit having the first value to each of the erased cells than to write a binary bit having a second value to said each of the erased cells.

15. The method of claim 13, wherein step (f) includes the steps of:

generating polarity flag bits for the encoded packets, wherein the polarity flag bits includes a set of at least one polarity flag bit for each of the encoded packets, and each said set of at least one polarity flag bit is indicative of which of the first encoding operation and the second encoding operation was performed to generate said each of the encoded packets; and

writing the polarity flag bits to a second subset of the erased cells of the array.

16. The method of claim 13, wherein step (f) includes the steps of:

writing a first one of the encoded packets to cells of the first subset array while performing at least steps (b) and (c) on a second one of the encoded packets.

17. A method for encoding binary bits to be written to erased cells of an array of flash memory cells, wherein each of the flash memory cells is capable of storing a binary bit, said method including the steps of:

(a) generating count signals from packets of the bits, wherein the count signals include a count signal for each of the packets indicative of how many bits of each of the packets have a selected binary value, and wherein the count signal for each of the packets is generated from data indicative of the number of bits in each of at least two subsets of each of the packets which have said selected binary value; and

(b) performing an encoding operation on each of the packets to generate an encoded packet of binary bits for each of the packets, wherein each said encoding operation is determined by the count signal for each of the packets.

18. The method of claim 17, also including the step of:

writing the encoded packets to a first subset of the erased cells of the array.

19. A method for controlling a flash memory system, wherein the system includes an array of flash memory cells and circuitry which erases selected blocks of the cells and writes packets of binary bits to erased ones of the cells, wherein the system consumes less power to write a binary bit having a first value to an erased one of the cells than to write a binary bit having a second value to said erased one of the cells, said method including the steps of:

(a) determining how many of the bits in each of the packets of bits have a first one of said first value and said second value by generating data indicative of the number of bits in each of at least two subsets of said each of the packets which have said first one of the first value and the second value, and generating count data indicative of said determination; and

(b) generating an encoded packet of binary bits from each of the packets, wherein each said encoded packet has a selected one of two polarities based on the count data indicative of the determination of how many of the bits in each of the packets have the first one of said first value and said second value.

20. The method of claim 19, wherein step (a) includes the steps of:

generating count signals from a sequence of the subsets of each of the packets, said count signals including a count signal for each of the subsets indicative of how many bits of each of the subsets have said first one of said first value and said second value; and

generating from the count signals for each one of the packets a packet count signal indicative of how many bits of said one of the packets of bits have said first one of said first value and said second value.

21. The method of claim 19, wherein step (b) includes the steps of:

comparing the packet count signal for each of the packets to a reference value;

generating a status signal as a result of each such comparison; and

generating the encoded packet for each of the packets in response to the status signal.

22. The method of claim 19, also including the steps of:

(c) generating a polarity bit for each said encoded packet, said polarity bit being indicative of the selected one of the two polarities for said encoded packet;

(d) storing each said polarity bit in a shift register; and

(e) writing each said encoded packet, and each said polarity bit, to erased ones of the cells.

23. The method for claim 19, wherein step (b) includes the steps of:

inverting each of the packets in response to the count data for each of the packets indicating a determination that each of the packets includes more bits having the second value than bits having the first value.

24. A memory system, including:

an array of flash memory cells, wherein the system consumes less power to write a binary bit having a first value to an erased one of said cells than to write a binary bit having a second value to said erased one of the cells; and

encoding circuitry coupled to receive X-bit packets of binary bits and configured to generate X-bit packets of encoded binary bits from the X-bit packets of binary bits, such that each of the packets of encoded binary bits consists of P encoded binary bits having the first value and Q encoded binary bits having the second value, where X, P, and Q are integers satisfying X=P+Q, and P is not less than Q, wherein the encoding circuitry includes;

count generation circuitry coupled to receive the packets and configured to generate count signals, wherein a count signal is generated for each of the packets by accumulating data indicative of the number of bits which have a first one of the first value and the second value in each of a number of subsets of each of the packets, and each said count signal is indicative of how many bits of the corresponding one of the packets have a first one of the first value and the second value;

a processor coupled to receive the count signals and configured to generate a first control signal for each of the count signals which satisfies a first criterion and a second control signal for each of the count signals which satisfies a second criterion; and

packet encoding circuitry coupled to receive each said first control signal and each said second control signal and configured to encode the packets in response to each said first control signal and each said second control signal, wherein the packet encoding circuitry performs a first encoding operation on each of the packets represented by said first control signal and a second encoding operation on each of the packets represented by said second control signal.

25. The system of claim 24, also including:

interface circuitry which writes the X-bit packets of encoded binary bits to erased flash memory cells of the array.

26. The system of claim 25, wherein the interface circuitry also includes circuitry which reads packets of encoded binary bits from the array, and wherein the system also includes:

decoding circuitry which decodes each of the packets of encoded binary bits read from the array.

27. The system of claim 25, also including:

a control engine which is configured to assert a selected one of an enable signal and a disable signal to the encoding circuitry, and wherein the encoding circuitry operates in an active mode which consumes power in response to the enable signal and in an inactive mode which consumes less power in response to the disable signal.

28. A memory system, including:

an array of flash memory cells, wherein the system consumes less power to write a bit having a first value to an erased one of said cells than to write a bit having a second value to said erased one of the cells;

a buffer memory which stores a number of X-bit packets of binary bits, where X is an integer;

a control engine which asserts a sequence of control signals in response to a command and a sequence of status signals, wherein the control engine is configured to generate a first one of the control signals in response to a first one of the status signals;

a conversion circuit connected to the buffer memory which receives a sequence of subsets of each of the packets and generates a count signal for each of the subsets indicative of how many binary bits of said each of the subsets have a first one of said first value and said second value; and

logic circuitry which operates in a first mode in response to a second one of the control signals in which it receives each said count signal for one of the packets and generates therefrom a packet count signal indicative of how many binary bits of said one of the packets have said first one of said first value and said second value, wherein the logic circuitry operates in a second mode in response to a third one of the control signals in which it compares the packet count signal to a reference value, generates said first one of the status signals as a result of the comparison, and asserts said first one of the status signals to the control engine, and wherein the logic circuitry operates in a third mode in response to the first one of the control signals in which it performs a first encoding operation on said one of the packets thereby generating an X-bit packet of encoded binary bits.

29. The system of claim 28, wherein the first one of the control signals indicates that said one of the packets consists of more binary bits having the second value than binary bits having the first value, and wherein said packet of encoded binary bits consists of more binary bits having the first value than binary bits having the second value.

30. The system of claim 28, wherein the first one of the status signals indicates that the packet count signal has a value that does not exceed the reference value, and

wherein said first encoding operation is the identity operation, so that said X-bit packet of encoded binary bits is identical to said one of the packets of binary bits.

31. The system of claim 28, also including:

a storage unit connected to the control engine, wherein the control engine generates first code data, and stores the first code data in the storage unit, in response to determining that the first one of the status signals indicates that the packet count signal has a value exceeding the reference value, and

wherein the control engine generates second code data, and stores the second code data in the storage unit, in response to determining that the first one of the status signals indicates that the packet count signal has a value that does not exceed the reference value.

32. The system of claim 28, wherein the first encoding operation consists of inverting each of the binary bits of one of the packets.

33. The system of claim 32, wherein each of the flash memory cells is a floating-gate N-channel transistor which stores a binary bit and is indicative of said first value when erased, and wherein said packet of encoded binary bits consists of more binary bits having the first value than binary bits having the second value.

34. The system of claim 33, wherein the first encoding operation consists of inverting each of the binary bits of one of the packets.

35. The system of claim 28, also including:

interface circuitry connected to the logic circuitry and to the control engine, wherein the interface circuitry writes the packet of encoded binary bits to erased flash memory cells of the array in response to receiving said packet of encoded binary bits from the logic circuitry and at least one of the control signals from the control engine.

36. A memory system, including:

an array of flash memory cells, each of the cells being capable of storing a binary bit;

count generation circuitry which receives packets of binary bits and generates count signals therefrom, wherein the count generation circuitry generates for each of said packets a count signal indicative of how many binary bits of said each of the packets have a selected value by accumulating data indicative of the number of bits which have the selected value in each of a number of subsets of said each of the packets;

encoding circuitry which receives each of the packets of binary bits and performs an encoding operation on said each of the packets of binary bits to generate a packet of encoded binary bits, wherein the encoding operation is determined by the count signal for said each of the packets of binary bits;

a control engine which asserts a sequence of control signals in response to a command; and

interface circuitry, connected to the array and the encoding circuitry, which writes each said packet of encoded binary bits to erased flash memory cells of the array in response to at least one of the control signals from the control engine.

37. The system of claim 36, also including:

an error detection and correction circuit coupled to receive the packets of binary bits and configured to operate in a first mode in which it generates check bits in response to the packets of binary bits and asserts the check bits to the interface circuitry, and wherein the interface circuitry writes the check bits to the array in response to at least one of the control signals from the control engine.

38. The system of claim 37, wherein the interface circuitry also includes circuitry which reads packets of encoded binary bits from the array, and wherein the system also includes:

decoding circuitry which decodes each of the packets of encoded binary bits read from the array, and wherein the error detection and correction circuit is coupled to receive packets of decoded bits that have been generated by the decoding circuitry, and is configured to operate in a second mode in which said error detection and correction circuit processes check bits of the packets of decoded bits to perform error detection and correction on said packets of decoded bits.

39. A controller for a flash memory system, wherein the system includes an array of flash memory cells and circuitry configured to erase selected blocks of the cells and to write packets of bits to erased ones of the cells, wherein the system consumes less power to write a bit having a first value to an erased one of the cells than to write a bit having a second value to said erased one of the cells, said controller including:

a first circuit coupled to receive the packets of bits and configured to determine how many of the bits in each of said packets of bits have a first one of the first value and the second value by accumulating data indicative of the number of bits which have the first one of the first value and the second value in each of a number of subsets of said each of the packets, and to generate count data indicative of said determination; and

a second circuit coupled to receive the packets of bits and configured to generate a packet of encoded bits from each of said packets of bits, wherein each said packet of encoded bits has a selected one of two polarities based on the count data indicative of the determination of how many of the bits in said each of the packets of bits have the first one of said first value and said second value.

40. The controller of claim 39, wherein the first circuit includes:

a conversion circuit coupled to receive a sequence of the subsets of said each of the packets of bits and configured to generate count signals therefrom, said count signals including a count signal for each of the subsets indicative of how many bits of said each of the subsets have said first one of said first value and said second value; and

logic circuitry configured to operate in a first mode in which it receives the count signals for one of the packets of bits and generates therefrom a packet count signal indicative of how many bits of said one of the packets of bits have said first one of said first value and said second value.

41. The controller of claim 40, wherein the logic circuitry is also configured to operate in a second mode in which it compares the packet count signal to a reference value and generates a status signal as a result of the comparison, wherein the second circuit generates the packet of encoded bits from said one of the packets of bits in response to the status signal.

42. The controller of claim 41, also including:

a third circuit coupled to receive each said packet of encoded bits and configured to generate a polarity bit for each said packet of encoded bits, said polarity bit being indicative of the selected one of the two polarities for said packet of encoded bits; and

a register for storing each said polarity bit while the system writes the packets of encoded bits to the erased ones of the cells.

43. The controller of claim 42, also including

a fourth circuit coupled to the array and configured to read polarity bits from the array and store said polarity bits in the register.

44. The controller of claim 39, wherein the second circuit includes:

logic circuitry which operates in a mode in which it inverts each of the packets of bits in response to the count data for said each of the packets of bits indicating a determination that said each of the packets of bits includes more bits having the second value than bits having the first value.

45. A count generation circuit for use in a flash memory system, wherein the system includes an array of flash memory cells and circuitry configured to erase selected blocks of the cells and write packets of bits to erased ones of the cells, wherein the system consumes less power to write a bit having a first value to an erased one of the cells than to write a bit having a second value to said erased one of the cells, said count generation circuit including:

a converter circuit configured to operate in a first mode in which it receives a sequence of subsets of bits of the packets and asserts count data in response to each of the subsets, wherein the count data for said each of the subsets is indicative of how many of the bits in said each of the subsets have a first one of said first value and said second value; and

a count circuit which processes the count data for all the subsets of one of the packets, thereby generating packet count data indicative of how many of the bits in said one of the packets have said first one of said first value and said second value.

46. The count generation circuit of claim 45, wherein the count circuit includes:

an adder having an output, a first input, and a second input, wherein the first input receives the count data from the converter circuit; and

an accumulator register having an input connected to the output of the adder, and an output connected to the second input of the adder.

47. The count generation circuit of claim 45, also including:

control circuitry which controls the adder to cause said adder to add each said count data from the converter circuit to data stored in the accumulator register thereby generating sum data, and which controls the adder to cause said adder to assert each said sum data to the accumulator register thereby updating data stored in the accumulator register.

48. The count generation circuit of claim 47, wherein the control circuitry resets the accumulator register after the count circuit has processed the count data for all the subsets of one of the packets.

49. The count generation circuit of claim 45, wherein the converter circuit operates in the first mode only in response to an enable signal from a control circuit.

50. The count generation circuit of claim 45, wherein the converter circuit receives the bits of each of the subsets of bits in parallel, said each of the subsets consists of eight bits of one of the packets, and the count data for said each of the subsets consists of four count bits.

51. The count generation circuit of claim 45, wherein the converter circuit includes:

a first partial count circuit which receives in parallel a set of least significant bits of said each of the subsets, and asserts in response first partial count data;

a second partial count circuit which receives in parallel a set of most significant bits of said each of the subsets, and asserts in response second partial count data; and

a multi-bit adder which adds the first partial count data to the second partial count data, thereby generating said count data for said each of the subsets.

52. The count generation circuit of claim 45, wherein the converter circuit is a look-up table memory which outputs said count data for said each of the subsets in response to being addressed by said each of the subsets.