Low voltage, high current pump for flash memory

• US 5,874,849 A
• Filed: 07/19/1996
• Issued: 02/23/1999
• Est. Priority Date: 07/19/1996
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Piersimoni, Pietro, Smayling, Michael C., Santin, Giovanni, Marotta, Giulio
• Primary Examiner(s): Wells, Kenneth B.
• Application Number:
  US08/684,652
• Time in Patent Office: 949 Days
• Field of Search: 327/536, 363/59, 363/60, 307/110
• US Class Current: 327/536
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type

Abstract

A charge pump 1 for operation in an integrated circuit having a power source Vdd. The pump is made of a plurality of pump cells 10 connected together. Each pump cell includes an inverter 50 having a port 42 to receive a negative bias input, a port 44 to receive a positive bias input, a port 38 to receive a clock input, and a port 40 to output an output clock signal at the same frequency of the clock input, but phase shifted by a predetermined amount determined by the signal levels of the negative bias and said positive bias. Also included in each pump cell is a capacitor 26. A circuit 20, 22, 24, for coupling the output clock signal to one port of the capacitor is also provided, as is a pair of diodes 28, 30, connected serially together, one end of the pair being connected to the power source and the other end 48 of the pair providing the output signal of the pump cell, the common point of the pair being connected to the other port of the capacitor. The pump cells are connected together such that the inverters are connected together to form a ring oscillator and such that the output signals are connected in parallel. The pump provides a stable source of high current at a moderately boosted voltage, with very low ripple, and is suitable for use with non-volatile, programmable memories.

Claims

1. A charge pump for operation in an integrated circuit having a power supply node providing a predetermined polarity voltage with respect to an electrical ground node, comprising a plurality of pump cells, each pump cell comprising:

a logical inverter having a first polarity power connection and having a second polarity power connection, configured to receive a clock input, and to provide an output clock signal that is inverted with respect to said clock input;

a first FET having a source and a drain connected between said first polarity power connection and said ground node, and having a gate receiving a first bias input;

a second FET having a source and a drain connected between said second polarity power connection and said power supply node, and having a gate receiving a second bias input;

a logic gate having a first input receiving said clock output, having a second input receiving a control signal, and having an output port,

a capacitor having a first port and a second port;

a buffer circuit for coupling said output port of said gate to said first port of said capacitor; and

a pair of diodes, each of said diodes comprising a bipolar transistor wired so as to include a short circuit between its base and collector so as to operate as a diode, said pair of diodes being connected serially together, one end of said pair being connected to said power supply node, and the other end of said pair being an output node for said pump cell and providing the output signal of said pump cell, the common point of said pair being connected to said second port of said capacitor;

said logical inverters being connected together to form a ring oscillator such that said output nodes are connected together, and such that said ring oscillator is connectable to each of said buffer circuits by assertion of said control signal.