Method and apparatus for driving a plurality of displays simultaneously

• US 5,874,928 A
• Filed: 08/24/1995
• Issued: 02/23/1999
• Est. Priority Date: 08/24/1995
• Status: Expired due to Term

• Current Assignee: MaxLinear Communications, LLC (f/k/a Entropic Communications, LLC) (Maxlinear Incorporated)
• Original Assignee: Philips Electronics North America Corporation (Koninklijke Philips N.V.)
• Inventors: Kou, Wallace
• Primary Examiner(s): Saras, Steven J.
• Assistant Examiner(s): LEWIS, DAVID LEE
• Application Number:
  US08/519,142
• Time in Patent Office: 1,279 Days
• Field of Search: 345/3, 345/89, 345/98, 345/200, 345/1, 345/153, 345/154, 345/155, 345/2, 364/237.3, 364/927.4, 395/750
• US Class Current: 345/1.1
• CPC Class Codes: G06F 3/1475 with conversion of CRT control signals to flat panel control signals, e.g. adapting the palette memory
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2360/04 Display device controller operating with a plurality of display units
• CPC Class Codes: G09G 3/2051 with use of a spatial dither pattern

Abstract

A method and apparatus for a display controller connected to a host computer and driving a plurality of displays, the displays being refreshed independently for optimizing the viewing quality of each display. The invention further provides a power controller for reducing power consumption when the display memory is not being updated by the host computer.

Claims

1. A method for driving a plurality of displays simultaneously, comprising the steps of:

(a) producing a first graphics data stream from a display memory at a rate determined by a first clock signal having a first clock rate;

(b) converting the first graphics data stream into a first video data stream at a rate determined by the first clock signal, the first video data stream having an analog portion and a digital portion;

(c) sending the analog portion of the first video data stream to a first video receiver for display;

(d) converting the digital portion of the first video data stream into a second video data stream for display by a second video receiver wherein the step (d) comprises the steps of;

i. converting the digital portion of the first video data stream into a second stream of graphics data at a rate determined by the first clock signal;

ii. storing the second stream of graphics data into a write buffer at a rate determined by the first clock signal;

iii. storing the second stream of graphics data from the write buffer into a frame buffer at a rate determined by a second clock signal having a second clock rate, the second clock rate being independent of the first clock rate;

iv. transferring graphics data from the frame buffer into a read buffer at a rate determined by the second clock signal;

v. producing a third stream of graphics data from the read buffer at a rate determined by the second clock signal;

vi. dithering the third stream of graphics data from the read buffer at a rate determined by the second clock signal to derive a set of dithered data;

vii. converting the dithered data to a second stream of video data at a rate determined by a second clock signal and;

viii. sending the second stream of video data to a second video receiver for display.

2. The method of claim 1, wherein the step of converting the first graphics data stream into a first video data stream comprises the steps of:

(a) applying the first graphics data stream as an index to a look-up table; and

(b) outputting data from the look-up table to a digital-to-analog converter.

3. The method of claim 1, wherein the step of converting the first graphics data stream into a first stream of video data comprises the step of:

(a) applying the first graphics data stream to a digital-to-analog converter.

4. The method of claim 1, wherein the step of converting the first graphics data stream into a first stream of video data comprises the steps of:

(a) applying the first graphics data stream as an index to a look-up table; and

(b) outputting data from the look-up table to an R-F modulator.

5. The method of claim 1, wherein the step of converting the digital portion of the first video data stream into a second stream of graphics data comprises the step of:

(a) processing the digital portion of the first video data stream in accordance with a selected weighting function to derive a set of weighted data.

6. The method of claim 1, wherein the step of converting the digital portion of the first video data stream into a second stream of graphics data further comprises the step of:

(a) processing the weighted data through a programmable mapping function to translate the weighted data into the second stream of graphics data.

7. The method of claim 1, further comprising the steps of:

(a) determining whether the display memory has been updated for a predetermined period of time; and

(b) suspending transference of data into the frame buffer if the display memory has not been updated for a predetermined period of time.

8. An apparatus for driving a plurality of displays simultaneously, comprising:

(a) a display memory for storing a first set of graphics data;

(b) a graphics buffer coupled to the display memory for receiving and storing a first stream of graphics data from the display memory, the graphics buffer outputting the first stream of graphics data stored therein at a rate determined by a first clock signal having a first clock rate;

(c) a data serializer coupled to the graphics buffer for receiving and processing the first graphics data stream to derive a stream of serialized graphics data at a rate determined by the first clock signal;

(d) a first converter coupled to the data serializer for receiving and converting the serialized graphics data stream into a first video data stream at a rate determined by the first clock signal, the first video data stream having an analog portion and a digital portion;

(e) a second converter coupled to the first converter for receiving and converting the digital portion of the first video data stream into a second serialized stream of graphics data at a rate determined by the first clock signal;

(f) a write buffer coupled to the second converter for receiving and storing the second stream of graphics data from the second converter at a rate determined by the first clock signal, the write buffer outputting the second stream of graphics data stored therein at a rate determined by a second clock signal, the second clock rate being independent from the first clock rate;

(g) a frame buffer coupled to the write buffer for receiving and storing the second stream of graphics data from the write buffer, the frame buffer outputting the graphics data stored therein as a third stream of graphics data at a rate determined by the second clock signal;

(h) a read buffer coupled to the frame buffer for receiving and storing the third stream of graphics data from the frame buffer, the read buffer outputting the third stream of graphics data at a rate determined by the second clock signal;

(i) a first controller coupled to the write buffer, the frame buffer and the read buffer for initiating the transfer of data between the buffers at a rate determined by the second clock signal;

(j) a dithering engine coupled to the read buffer for receiving and processing the third stream of graphics data from the read buffer to derive a second video data stream at a rate determined by the second clock signal; and

(k) a second controller coupled to the dithering engine and the read buffer for initiating and controlling the conversion of the third stream of graphics data into the second video data stream.

9. The apparatus of claim 8, wherein the analog portion of the first video data stream is coupled to a first display and the second video data stream is coupled to a second display.

10. The apparatus of claim 8, wherein the display memory and the frame buffer are two separate memories.

11. The apparatus of claim 8, wherein the display memory and the frame buffer are separate portions of a single memory.

12. The apparatus of claim 8, wherein the first converter comprises:

a look-up table memory having a data output; and

a digital-to-analog converter coupled to the data output of the look-up table memory.

13. The apparatus of claim 8, wherein the first converter comprises an RF modulator.

14. The apparatus of claim 8, wherein the second converter comprises:

(a) means for processing the digital portion of the first video data stream in accordance with a selected weighting function to derive a set of weighted data; and

(b) means for translating the weighted data into the second serialized stream of graphics data which is customized for a second video display.

15. The apparatus of claim 8, further comprising:

(a) a controller coupled to the display memory for determining whether the display memory has been updated with new graphics data within a predetermined period of time, the controller suspending transference of data into the frame buffer, thereby reducing power consumption, in response to a determination that the display memory has not been updated with new graphics data within a predetermined period of time.

16. An apparatus for driving a plurality of displays simultaneously, comprising:

(a) a display memory for storing a first set of graphics data;

(b) a graphics buffer coupled to the display memory for receiving and storing a first stream of graphics data from the display memory, the graphics buffer outputting the first stream of graphics data stored therein at a rate determined by a first clock signal having a first clock rate;

(c) a data serializer coupled to the graphics buffer for receiving and processing the first graphics data stream to derive a stream of serialized graphics data at a rate determined by the first clock signal;

(d) a first converter coupled to the data serializer for receiving and converting the serialized graphics data stream into a first video data stream at a rate determined by the first clock signal, the first video data stream having an analog portion and a digital portion;

(e) a second converter coupled to the first converter for receiving and converting the digital portion of the first video data stream into a second serialized stream of graphics data at a rate determined by the first clock signal;

(f) a write buffer coupled to the second converter for receiving and storing the second stream of graphics data from the second converter at a rate determined by the first clock signal, the write buffer outputting the second stream of graphics data stored therein at a rate determined by a second clock signal, the second clock rate being independent from the first clock rate;

(g) a frame buffer coupled to the write buffer for receiving and storing the second stream of graphics data from the write buffer, the frame buffer outputting the graphics data stored therein as a third stream of graphics data at a rate determined by the second clock signal;

(h) a read buffer coupled to the frame buffer for receiving and storing the third stream of graphics data from the frame buffer, the read buffer outputting the third stream of graphics data at a rate determined by the second clock signal;

(i) a first controller coupled to the write buffer, the frame buffer and the read buffer for initiating the transfer of data between the buffers at a rate determined by the second clock signal;

(j) a dithering engine coupled to the read buffer for receiving and processing the third stream of graphics data from the read buffer to derive a second video data stream at a rate determined by a third clock signal, the third clock signal being independent of the first clock signal and the second clock signal; and

(k) a second controller coupled to the dithering engine and the read buffer for initiating and controlling the conversion of the third stream of graphics data into the second video data stream at a rate determined by the third clock signal.

17. The apparatus of claim 16, wherein the analog portion of the first video data stream is coupled to a first display and the second video data stream is coupled to a second display.

18. The apparatus of claim 16, wherein the display memory and the frame buffer are two separate memories.

19. The apparatus of claim 16, wherein the display memory and the frame buffer are separate portions of a single memory.

20. The apparatus of claim 16, wherein the first converter comprises:

a look-up table memory having a data output; and

a digital-to-analog converter coupled to the data output of the look-up table memory.

21. The apparatus of claim 16, wherein the first converter comprises an RF modulator.

22. The apparatus of claim 16, wherein the second converter comprises:

i. means for processing the digital portion of the first video data stream in accordance with a selected weighting function to derive a set of weighted data; and

ii. means for translating the weighted data into the second serialized stream of graphics data which is customized for a second video display.

23. The apparatus of claim 16, further comprising:

i. a controller coupled to the display memory for determining whether the display memory has been updated with new graphics data within a predetermined period of time, the controller suspending transference of data into the frame buffer, thereby reducing power consumption, in response to a determination that the display memory has not been updated with new graphics data within a predetermined period of time.

24. An integrated circuit for driving a plurality of displays, the integrated circuit coupled to a display memory and a frame buffer, and comprising:

(a) a graphics buffer coupled to the display memory for receiving and storing a first stream of graphics data from the display memory, the graphics buffer outputting the first stream of graphics data stored therein at a rate determined by a first clock signal having a first clock rate;

(b) a data serializer coupled to the graphics buffer for receiving and processing the graphics data stream to derive a stream of serialized graphics data at a rate determined by the first clock signal;

(c) a first converter coupled to the data serializer for receiving and converting the serialized graphics data stream into a first video data stream at a rate determined by the first clock signal;

(d) a second converter coupled to the first converter for receiving and converting the video data stream into a second serialized stream of graphics data at a rate determined by the first clock signal;

(e) a write buffer coupled to the second converter for receiving and storing the second stream of graphics data from the second converter at a rate determined by the first clock signal, the write buffer outputting the second stream of graphics data stored therein at a rate determined by a second clock signal, the second clock rate being independent from the first clock rate;

(f) a frame buffer coupled to the write buffer for receiving and storing the second stream of graphics data from the write buffer, the frame buffer outputting the graphics data stored therein as a third stream of graphics data at a rate determined by the second clock signal;

(g) a read buffer coupled to the frame buffer for receiving and storing the third stream of graphics data from the frame buffer, the read buffer outputting the third stream of graphics data at a rate determined by the second clock signal

(h) a first controller coupled to the write buffer, the frame buffer and the read buffer for initiating the transfer of data between the buffers at a rate determined by the second clock signal;

(i) a dithering engine coupled to the read buffer for receiving and processing the third stream of graphics data from the read buffer to derive a second video data stream at a rate determined by the second clock signal;

(j) a second controller coupled to the dithering engine and the read buffer to initiate the transfer and conversion of the third stream of graphics data to a second video data stream.

25. An integrated circuit for driving a plurality of displays, the integrated circuit coupled to a display memory and a frame buffer, and comprising:

(a) a graphics buffer coupled to the display memory for receiving and storing a first stream of graphics data from the display memory, the graphics buffer outputting the first stream of graphics data stored therein at a rate determined by a first clock signal having a first clock rate;

(b) a data serializer coupled to the graphics buffer for receiving and processing the graphics data stream to derive a stream of serialized graphics data at a rate determined by the first clock signal;

(c) a first converter coupled to the data serializer for receiving and converting the serialized graphics data stream into a first video data stream at a rate determined by the first clock signal;

(d) a second converter coupled to the first converter for receiving and converting the video data stream into a second serialized stream of graphics data at a rate determined by the first clock signal;

(e) a write buffer coupled to the second converter for receiving and storing the second stream of graphics data from the second converter at a rate determined by the first clock signal, the write buffer outputting the second stream of graphics data stored therein at a rate determined by a second clock signal, the second clock rate being independent from the first clock rate;

(f) a frame buffer coupled to the write buffer for receiving and storing the second stream of graphics data from the write buffer, the frame buffer outputting the graphics data stored therein as a third stream of graphics data at a rate determined by the second clock signal;

(g) a read buffer coupled to the frame buffer for receiving and storing the third stream of graphics data from the frame buffer, the read buffer outputting the third stream of graphics data at a rate determined by the second clock signal

(h) a first controller coupled to the write buffer, the frame buffer and the read buffer for initiating the transfer of data between the buffers at a rate determined by the second clock signal;

(i) a dithering engine coupled to the read buffer for receiving and processing the third stream of graphics data from the read buffer to derive a second video data stream at a rate determined by a third clock signal, the third clock signal being independent of the first clock signal and the second clock signal; and

(j) a second controller coupled to the dithering engine and the read buffer to initiate the transfer and conversion of the third stream of graphics data to a second video data stream at a rate determined by a third clock signal.