Sample hold circuit for LCD driver

• US 5,874,934 A
• Filed: 12/17/1996
• Issued: 02/23/1999
• Est. Priority Date: 12/20/1995
• Status: Expired due to Term

• Current Assignee: Vista Peak Ventures LLC (Dominion Harbor Enterprises, LLC)
• Original Assignee: NEC Corporation
• Inventors: Ito, Masahiro
• Primary Examiner(s): Hjerpe, Richard A.
• Assistant Examiner(s): Tran, Henry N.
• Application Number:
  US08/767,844
• Time in Patent Office: 798 Days
• Field of Search: 345/98, 345/100, 345/99, 345/89
• US Class Current: 345/98
• CPC Class Codes: G09G 2310/0297 Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3688 suitable for active matrices only

Abstract

In order to provide a sample hold circuit used in LCD driver circuit or dividing an analog signal to parallel source driving signals in desired order with fewer numbers of elements and lower current consumption, a sample hold circuit of the invention comprises two emitter coupling logic circuit (2 and 3), each having the same number of transistors (Q2-1 to Q2-n and Q3-1 to Q3-n) with their bases controlled with outputs of a shift register (6). By connecting collectors of transistors (Q2-1 to Q2-n and Q3-1 to Q3-n) of each emitter coupling logic circuit (2 or 3) to current mirrors (4-1 to 4-n) in inverse order with each other, sample hold units (5-1 to 5-n) output sample hold signals supplied with outputs of the current mirrors (4-1 to 4-n) forward scanning or backward scanning according to the emitter coupling logic circuit (1 or 2) activated.

Claims

1. A sample hold circuit comprising:

a first emitter coupling logic circuit having a first and a second transistor, coupled emitters of said emitter coupling logic circuit grounded through biasing means and each base of said first and said second transistor supplied with each of complimentary scanning signals;

a second emitter coupling logic circuit having n transistors, coupled emitters of said second emitter coupling logic circuit connected to a collector of said first transistor, n being a positive integer;

a third emitter coupling logic circuit having n transistors, coupled emitters of said third emitter coupling logic circuit connected to a collector of said second transistor;

a shift register 6 for generating n timing pulses by shifting a start pulse synchronized with a dot clock, each i-th of said n timing pulses delayed by i clock cycle(s) from said start pulse and delivered to bases of i-th transistors of said second and said third emitter coupling logic circuits, i being a positive integer until n;

a sample hold section 5 for dividing an analog signal into parallel signals having n sample hold units, each of said n sample hold units outputting a parallel signal held therein by sampling said analog signal when a sampling signal is delivered thereto; and

a current amplifying section 4 having n current amplifying means supplied with a power supply, each i-th of said n current amplifying means delivering said sampling signal to corresponding i-th of said n sample hold units when current flows through an input line thereof connected to a collector of corresponding i-th of said n transistors of said second emitter coupling logic circuit 2 together with a collector of corresponding (n-i+1)-th of said n transistors of said third emitter coupling logic circuit 3.

2. A sample hold circuit recited in claim 1, wherein each of said n current amplifying means is a current mirror circuit.

3. A sample hold circuit recited in claim 1, wherein said biasing means is a constant current circuit.

4. A sample hold circuit recited in claim 1, wherein said biasing means is a resistor.