MPEG video decoder having a high bandwidth memory for use in decoding interlaced and progressive signals

• US 5,874,995 A
• Filed: 09/02/1997
• Issued: 02/23/1999
• Est. Priority Date: 10/28/1994
• Status: Expired due to Term

• Current Assignee: Panasonic Corporation Of North America (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Corporation Of America (Panasonic Holdings Corporation)
• Inventors: Inoue, Shuji, Naimpally, Saiprasad V.
• Primary Examiner(s): RAO, ANAND SHASHIKANT
• Application Number:
  US08/923,549
• Time in Patent Office: 539 Days
• Field of Search: 348/717, 348/715, 348/718, 348/719, 348/415, 348/416, 348/405, 348/384, 348/423, 348/464, 348/419, 348/411, 348/412, 348/854.1-3
• US Class Current: 375/240.25
• CPC Class Codes: H04N 19/13 Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
• CPC Class Codes: H04N 19/174 the region being a slice, e.g. a line of blocks or a group of blocks
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/436 using parallelised computational arrangements
• CPC Class Codes: H04N 19/44 Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/60 using transform coding
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 19/91 Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 5/04 Synchronising for television systems using pulse code modulation H04N7/56
• CPC Class Codes: H04N 7/012 Conversion between an interlaced and a progressive signal for graphics images G09G2310/0229
• CPC Class Codes: H04N 7/56 Synchronising systems therefor

Abstract

A decoder for a video signal encoded according to the MPEG-2 standard processes either interlace scan signals or progressive scan signals by dynamically reconfiguring a single high-bandwidth memory. The memory is used to hold 1) the input bit-stream, 2) first and second reference frames used for motion compensated processing, and 3) image data representing a field that is currently being decoded. The decoder includes circuitry which stores and fetches the bit-stream data, fetches the reference frame data, stores the image data for the field that is currently being decoded in block format and fetches this image data for conversion to raster-scan format. This circuitry also detects whether the signal is in interlace or progressive format from the input data stream. When an interlace format signal is being decoded, the memory is partitioned in one configuration and when a progressive format signal is being decoded, the memory is partitioned in another configuration.

Claims

1. Apparatus of decoding a variable length encoded data stream including a plurality of variable length encoded data values representing a plurality of image frames the variable length encoded data values being arranged in sequence records, each sequence record including variable length encoded data values representing a plurality of images, wherein each sequence record of the variable length encoded data stream includes a header and each sequence record represents either an interlaced signal which is to be displayed in interlaced format or a progressive signal which is to be displayed in progressive format, the apparatus comprising:

a memory having a configuration which partitions the memory into sections;

means for receiving the variable length encoded data stream and for storing the variable length encoded data stream into a first one of the sections of the memory;

decoding means including;

means for fetching the variable length encoded data stream from the first section of the memory;

means for processing the fetched variable length encoded data stream to produce first decoded values;

means for processing the sequence headers from the fetched variable length encoded data stream to produce a control signal which indicates whether the first decoded values are to be displayed in progressive format or in interlaced format;

means for fetching reference image data from a second one of the sections of the memory;

means for combining the fetched reference image data with the first decoded values to produce second decoded values which represent the current image; and

means for storing the second decoded values in a third one of the sections of the memory;

means for fetching image data from one of the second and third sections of the memory, for display; and

memory configuration means, responsive to the control signal, for changing the configuration of the memory between a configuration appropriate for decoding and displaying the interlaced signal and a configuration appropriate for decoding and displaying the progressive signal by changing relative amounts of memory allocated to said first section of the memory and to one of the said second and third sections of the memory, respectively.

2. Apparatus according to claim 1, wherein the memory configuration means adds memory to the first one of the sections of the memory and deletes memory from the third one of the sections of memory when changing the configuration of the memory from the configuration appropriate for decoding and displaying the interlaced signal to the configuration appropriate for decoding and displaying the progressive signal.

3. Apparatus according to claim 2, wherein the memory configuration means adds an amount of memory which holds approximately one-quarter frame of pixel data to the first one of the sections and deletes a corresponding amount of memory from the third one of the sections when changing the configuration of the memory from the configuration appropriate for decoding and displaying the interlaced signal to the configuration appropriate for decoding and displaying the progressive signal.

4. Apparatus according to claim 2, wherein the memory configuration means adds an amount of memory to the first one of the sections which is sufficient to increase the first one of the sections in size by approximately fifty percent and deletes a corresponding amount of memory from the third one of the sections when changing the configuration of the memory from the configuration appropriate for decoding and displaying the interlaced signal to the configuration appropriate for decoding and displaying the progressive signal.

12. The apparatus for decoding the data stream according to claim 1 wherein each of the second decoded values is a fully decoded image pixel value that may be retrieved to display a scene.

5. Apparatus for decoding a data stream including a plurality of variable length encoded data values representing a plurality of image frames of a video signal, the data stream including a plurality of sequence records, each sequence record having a header and each sequence record containing variable length encoded data values representing either an interlaced signal which is to be displayed in interlaced format or a progressive signal which is to be displayed in progressive format, the apparatus comprising:

a memory, having a configuration which defines a partitioning of the memory into distinct memory areas;

an input circuit which receives the data stream and stores the data stream into a first one of the memory areas;

a decoder which processes the received data stream to produce data representing a decoded image in block format, which processes the sequence headers of the received data stream to generate a scan-type control signal, the scan-type control signal indicating whether the data stream is to be decoded to produce progressive format image data or interlaced format image data, and which stores the decoded image that represents the current image into a second one of the memory areas in block format;

a block to raster converter, which retrieves the decoded image from the memory in block format and which converts the decoded images from block format to raster format; and

circuitry which configures the memory to allocate data areas suitable for decoding signals in either the progressive format or the interlaced format, responsive to the scan-type control signal by changing relative amounts of memory allocated to said first and second memory areas, respectively.

7. The apparatus for decoding the data stream according to claim 5 further comprising:

means for fetching reference image data from a third one of the memory areas; and

means for using the fetched reference image data to produce the decoded values.

8. The apparatus for decoding the data stream according to claim 5 wherein each of the decoded values is a fully decoded image pixel value that may be retrieved to display a scene.

6. Apparatus for decoding a data stream including a plurality of variable length encoded data values representing a plurality of image frames, wherein the data stream includes a plurality of sequence records, each sequence record having a header and each sequence record containing variable length encoded data values representing one of an interlaced scan image sequence and a progressive scan image sequence which is to be displayed in interlaced format, the apparatus comprising:

a memory, having a configuration which defines a partitioning of the memory into distinct memory areas;

an input circuit which receives the data stream and stores the data stream into a first one of the memory areas;

a decoder which processes the received data stream to produce data representing a decoded current image in block format, which processes the sequence headers of the received data stream to generate a scan-type control signal, the scan-type control signal indicating whether the data stream represents the interlaced scan image sequence or the progressive scan image sequence, and which stores blocks of the decoded image data, that represent respective portions of the current image, into a second one of the memory areas, as the blocks of decoded image data are produced;

a block to raster converter, which fetches blocks of decoded image data from the second memory area and converts the decoded images from block format to raster format; and

circuitry which configures the memory to allocate data areas suitable for decoding signals in either the progressive format or the interlaced format, responsive to the scan-type control signal by changing relative amounts of memory allocated to the first and second memory areas, respectively.

9. The apparatus for decoding the data stream according to claim 6 further comprising:

means for fetching reference image data from a third one of the memory areas; and

means for using the fetched reference image data to produce the decoded values during a first time interval and for providing the fetched reference image data to the block to raster converter during a second time interval.

10. The apparatus for decoding the data stream according to claim 6 wherein each of the decoded values is a fully decoded image pixel value that may be retrieved to display a scene.

11. Apparatus for decoding a data stream including a plurality of variable length encoded data values representing a plurality of image frames of a video signal, the data stream including a plurality of sequence records, each sequence record having a header and each sequence record containing variable length encoded data values representing one of an interlaced scan image and a progressive scan image which is to be displayed in interlaced format, the apparatus comprising:

memory, having a configuration which defines a partitioning of the memory into distinct memory areas;

an input circuit which receives the data stream and stores the data stream into a first one of the memory areas;

a decoder which processes the received data stream to produce data representing a decoded image in block format, which processes the sequence headers of the received data stream to generate a scan-type control signal the scan-type control signal indicating whether the data stream represents the interlaced scan image or the progressive scan image, and which stores the decoded image data, representing the current image, as the decoded image data is produced, in a second one of the memory areas;

circuitry which configures the memory to allocate data areas suitable for decoding signals in either the progressive format or the interlaced format, responsive to the scan-type control signal by changing relative amounts of memory allocated to the first and second memory areas, respectively; and

a block to raster converter, which converts the decoded images from block format to raster format, wherein when the scan-type control signal indicates that the data stream represents a progressive scan image, the block to raster converter fetches blocks of contiguous lines for each frame to be displayed and processes for display, only alternate ones of the lines from each fetched block.