Interconnect delay calculation apparatus and path delay value verification apparatus for designing semiconductor integrated circuit and circuit model data storage device

• US 5,875,114 A
• Filed: 02/13/1997
• Issued: 02/23/1999
• Est. Priority Date: 08/27/1996
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Kagatani, Tatsuji, Mani, Toshihiro
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US08/800,025
• Time in Patent Office: 740 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/578
• US Class Current: 716/113
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A circuit model is used which consists essentially of a common portion having an interconnect wire length percentage of A %, and a branch portion having an interconnect wire length percentage of (100-A) % and branched uniformly for each fan-out (n). An interconnect delay calculation apparatus calculates estimated interconnect delay values using data of a coefficient (A) previously determined for each fan-out (n) from past design data by a statistical technique on the basis of a delay calculation expression for the circuit model which is {A/100+(100-A)/(100n²)}Rw(Cw+Cp). The estimated interconnect delay values are calculated accurately when a semiconductor integrated circuit is designed.

Claims

1. An interconnect delay calculation apparatus for calculating estimated interconnect delay values for an interconnect wire length when an output of a first macro cell is connected to inputs of n second macro cells (n≧

1) in designing a semiconductor integrated circuit, said interconnect delay calculation apparatus comprising;

storage means for electrically storing therein predetermined data about a circuit model designed for said interconnect wire length and consisting essentially of a common portion and a branch portion with a fan-out of n, said common portion having a first resistance connected between said output of said first macro cell and a branch point, and a first capacitance connected between said branch point and ground, said branch portion including branch interconnect wires for connecting said branch point to said n second macro cells, respectively, and uniformly branched for the fan-out of n, each of said branch interconnect wires having a second resistance connected between said branch point and the input of a corresponding one of said second macro cells, a second capacitance serving as a parasitic capacitance and connected between the input of the corresponding one of said second macro cells and the ground, and a pin capacitance connected between the input of the corresponding one of said second macro cells and the ground, and

calculating means for electrically calculating said estimated interconnect delay values using a predetermined delay calculation expression specified by time constants of said first and second resistances, said first and second capacitances, and said pin capacitance on the basis of said predetermined data extracted from said storage means.

2. The interconnect delay calculation apparatus of claim 1,

wherein the lengths of said common portion and said branch portion are defined on a percentage basis respectively as a first coefficient and 100 minus said first coefficient, based upon said interconnect wire length of said circuit model,

wherein said first resistance, said second resistance, said first capacitance, and said second capacitance are defined respectively as said first coefficient times an estimated wiring resistance divided by 100, the quantity 100 minus said first coefficient times said estimated wiring resistance divided by 100n, said first coefficient times an estimated wiring capacitance divided by 100, and the quantity 100 minus said first coefficient times said estimated wiring capacitance divided by 100n,

wherein said storage means comprises

first storage means for storing therein circuit diagram data when said circuit model is applied to said interconnect wire length to be designed for said semiconductor integrated circuit,

second storage means for storing therein data about said pin capacitance for a plurality of types of semiconductor devices usable as said second macro cells as a library, and

third storage means for storing therein first coefficient table data indicative of information about said first coefficient, second coefficient table data indicative of a wiring resistance per unit interconnect wire length, third coefficient table data indicative of a wiring capacitance per unit interconnect wire length, and fourth coefficient table data indicative of an estimated interconnect wire length for each fan-out,

said circuit diagram data comprising both data about type information and pin information of said second macro cells contained in said interconnect wire length to be designed, and data about said fan-out of said interconnect wire length to be designed,

said estimated interconnect wire length being equal to the sum of the length of said common portion and the length of said branch portion,

said first and fourth coefficient table data being previously determined by a statistical technique, and

wherein said calculating means comprises

first extracting means for extracting the data about said type information and said pin information of said second macro cells from said first storage means to extract said pin capacitance data of said second macro cells from said second storage means on the basis of the extracted data,

first calculating means for electrically calculating the sum of said pin capacitance data extracted from said first extracting means,

second extracting means for extracting said fan-out data from said first storage means,

second calculating means for extracting corresponding ones of said first, second, third, and fourth coefficient table data from said third storage means on the basis of said fan-out data extracted by said second extracting means to electrically determine said extracted second, third, and fourth coefficient table data as second, third, and fourth coefficient data, respectively, to electrically calculate data of said estimated wiring resistance and data of said estimated wiring capacitance on the basis of the multiplication of said second and fourth coefficient data and the multiplication of said third and fourth coefficient data, respectively, and to electrically determine first coefficient data indicative of said first coefficient for said interconnect wire length to be designed on the basis of said first coefficient table data, and

third calculating means for electrically calculating said estimated interconnect delay values on the basis of output signals from said first and second calculating means by using said predetermined delay calculation expression specified based on said first coefficient data, said estimated wiring resistance data, said estimated wiring capacitance data, said pin capacitance sum data, and said fan-out data.

3. The interconnect delay calculation apparatus of claim 2,

wherein said first coefficient table data are previously determined for each fan-out by the statistical technique, and

wherein said second calculating means comprises

first coefficient determining means for selecting the presence/absence of said first coefficient table data corresponding to said fan-out on the basis of said fan-out data, said first coefficient determining means electrically determining said first coefficient table data as said first coefficient data required for calculation when said corresponding first coefficient table data are present, said first coefficient determining means electrically determining said first coefficient data required for calculation by electrical processing using linear interpolation when said corresponding first coefficient table data are absent.

4. The interconnect delay calculation apparatus of claim 2,

wherein said first coefficient table data are comprised of only constant data common to any fan-out and determined previously by the statistical technique, and

wherein said second calculating means comprises

first coefficient determining means for selecting said first coefficient table data on the basis of said fan-out data to electrically determine said first coefficient table data as said first coefficient data required for calculation.

5. The interconnect delay calculation apparatus of claim 2,

wherein said pin capacitance of each of said second macro cells in said circuit model is given by said pin capacitance sum data divided by said fan-out data, and

wherein said third calculating means comprises

estimated interconnect delay value calculating means for electrically calculating said estimated interconnect delay values on the basis of the output signals from said first and second calculating means by using said predetermined delay calculation expression specified by said first coefficient data, said estimated wiring resistance data, said estimated wiring capacitance data, said pin capacitance sum data divided by said fan-out data, and said fan-out data.

6. The interconnect delay calculation apparatus of claim 3,

wherein said pin capacitance of each of said second macro cells in said circuit model is given by said pin capacitance sum data divided by said fan-out data, and

wherein said third calculating means comprises

estimated interconnect delay value calculating means for electrically calculating said estimated interconnect delay values on the basis of the output signals from said first and second calculating means by using said predetermined delay calculation expression specified by said first coefficient data, said estimated wiring resistance data, said estimated wiring capacitance data, said pin capacitance sum data divided by said fan-out data, and said fan-out data.

7. The interconnect delay calculation apparatus of claim 4,

wherein said pin capacitance of each of said second macro cells in said circuit model is given by said pin capacitance sum data divided by said fan-out data, and

wherein said third calculating means comprises

estimated interconnect delay value calculating means for electrically calculating said estimated interconnect delay values on the basis of the output signals from said first and second calculating means by using said predetermined delay calculation expression specified by said first coefficient data, said estimated wiring resistance data, said estimated wiring capacitance data, said pin capacitance sum data divided by said fan-out data, and said fan-out data.

8. The interconnect delay calculation apparatus of claim 2,

wherein said pin capacitance of each of said second macro cells in said circuit model is given by corresponding ones of said pin capacitance data extracted by said first extracting means, and

wherein said third calculating means comprises

estimated interconnect delay value calculating means for electrically calculating each of said estimated interconnect delay values on the basis of the output signals from said first and second calculating means and an output signal of each of said pin capacitance data extracted by said first extracting means by using said predetermined delay calculation expression specified based on said first coefficient data, said estimated wiring resistance data, said estimated wiring capacitance data, said pin capacitance sum data, said fan-out data, and each of said pin capacitance data.

9. The interconnect delay calculation apparatus of claim 3,

wherein said pin capacitance of each of said second macro cells in said circuit model is given by corresponding ones of said pin capacitance data extracted by said first extracting means, and

wherein said third calculating means comprises

estimated interconnect delay value calculating means for electrically calculating each of said estimated interconnect delay values on the basis of the output signals from said first and second calculating means and an output signal of each of said pin capacitance data extracted by said first extracting means by using said predetermined delay calculation expression specified based on said first coefficient data, said estimated wiring resistance data, said estimated wiring capacitance data, said pin capacitance sum data, said fan-out data, and each of said pin capacitance data.

10. The interconnect delay calculation apparatus of claim 4,

wherein said pin capacitance of each of said second macro cells in said circuit model is given by corresponding ones of said pin capacitance data extracted by said first extracting means, and

wherein said third calculating means comprises

estimated interconnect delay value calculating means for electrically calculating each of said estimated interconnect delay values on the basis of the output signals from said first and second calculating means and an output signal of each of said pin capacitance data extracted by said first extracting means by using said predetermined delay calculation expression specified based on said first coefficient data, said estimated wiring resistance data, said estimated wiring capacitance data, said pin capacitance sum data, said fan-out data, and each of said pin capacitance data.

11. A path delay value verification apparatus for functioning to calculate a path delay value of a semiconductor integrated circuit when said semiconductor integrated circuit is designed, said path delay value verification apparatus comprising an interconnect delay calculation apparatus, said path delay value verification apparatus using said interconnect delay calculation apparatus to electrically calculate estimated interconnect delay values of individual interconnect wire lengths in said semiconductor integrated circuit, said interconnect delay calculation apparatus calculating estimated interconnect delay values for an interconnect wire length when an output of a first macro cell is connected to inputs of n second macro cells (n≧

1) in designing said semiconductor integrated circuit, said interconnect delay calculation apparatus comprising;

storage means for electrically storing therein predetermined data about a circuit model designed for said interconnect wire length and consisting essentially of a common portion and a branch portion with a fan-out of n, said common portion having a first resistance connected between said output of said first macro cell and a branch point, and a first capacitance connected between said branch point and ground, said branch portion including branch interconnect wires for connecting said branch point to said n second macro cells, respectively, and uniformly branched for the fan-out of n, each of said branch interconnect wires having a second resistance connected between said branch point and the input of a corresponding one of said second macro cells, a second capacitance serving as a parasitic capacitance and connected between the input of the corresponding one of said second macro cells and the ground, and a pin capacitance connected between the input of the corresponding one of said second macro cells and the ground, and

calculating means for electrically calculating said estimated interconnect delay values using a predetermined delay calculation expression specified by time constants of said first and second resistances, said first and second capacitances, and said pin capacitance on the basis of said predetermined data extracted from said storage means.

12. A circuit model data storage device for electrically holding predetermined data for calculating estimated interconnect delay values of a semiconductor integrated circuit,

wherein said predetermined data are data indicative of respective portions of a circuit model,

wherein said circuit model is designed for an interconnect wire length when an output of a first macro cell is connected to inputs of n second macro cells (n≧

1), and consists essentially of a common portion and a branch portion with a fan-out of n, said common portion having a first resistance connected between said output of said first macro cell and a branch point, and a first capacitance connected between said branch point and ground, said branch portion including branch interconnect wires for connecting said branch point to said n second macro cells, respectively, and uniformly branched for the fan-out of n, each of said branch interconnect wires having a second resistance connected between said branch point and the input of a corresponding one of said second macro cells, a second capacitance serving as a parasitic capacitance and connected between the input of the corresponding one of said second macro cells and the ground, and a pin capacitance connected between the input of the corresponding one of said second macro cells and the ground, and

wherein said data indicative of said respective portions correspond to data about said first and second resistances, said first and second capacitances, said pin capacitance, said fan-out, and the proportions of said common portion and said branch portion, based upon said interconnect wire length.

13. The circuit model data storage device of claim 12,

wherein the lengths of said common portion and said branch portion are defined on a percentage basis respectively as a first coefficient and 100 minus said first coefficient, based upon said interconnect wire length of said circuit model,

wherein said first resistance, said second resistance, said first capacitance, and said second capacitance are defined respectively as said first coefficient times an estimated wiring resistance divided by 100, the quantity 100 minus said first coefficient times said estimated wiring resistance divided by 100n, said first coefficient times an estimated wiring capacitance divided by 100, and the quantity 100 minus said first coefficient times said estimated wiring capacitance divided by 100n, and

wherein said predetermined data comprise

circuit diagram data,

data about said pin capacitance for a plurality of types of semiconductor devices usable as said second macro cells,

first coefficient table data indicative of information about said first coefficient,

second coefficient table data indicative of a wiring resistance per unit interconnect wire length,

third coefficient table data indicative of a wiring capacitance per unit interconnect wire length, and

fourth coefficient table data indicative of an estimated interconnect wire length for each fan-out,

said circuit diagram data comprising both data about type information and pin information of said second macro cells contained in said interconnect wire length to be designed, and data about said fan-out of said interconnect wire length to be designed,

said estimated interconnect wire length being equal to the sum of the length of said common portion and the length of said branch portion,

said first and fourth coefficient table data being previously determined by a statistical technique.